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author | Polina Dudnik <pdudnik@gmail.com> | 2009-08-14 17:57:54 -0500 |
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committer | Polina Dudnik <pdudnik@gmail.com> | 2009-08-14 17:57:54 -0500 |
commit | a8e11cf3bbb3cdb1e49a4bc0ae8e2e47fbc8400d (patch) | |
tree | 8dcdd829269f0774ccc408a44f64e75af41b6aee /src/mem/slicc/symbols/StateMachine.cc | |
parent | ee3226d973d696a5b0838364be649d0abd514c60 (diff) | |
download | gem5-a8e11cf3bbb3cdb1e49a4bc0ae8e2e47fbc8400d.tar.xz |
Bug fix: indicate when writes started coming in
Diffstat (limited to 'src/mem/slicc/symbols/StateMachine.cc')
-rw-r--r-- | src/mem/slicc/symbols/StateMachine.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.cc b/src/mem/slicc/symbols/StateMachine.cc index 99c1953a1..46047ec25 100644 --- a/src/mem/slicc/symbols/StateMachine.cc +++ b/src/mem/slicc/symbols/StateMachine.cc @@ -302,6 +302,7 @@ void StateMachine::printControllerH(ostream& out, string component) } if (strncmp(component.c_str(), "L1Cache", 7) == 0) { out << " bool servicing_atomic;" << endl; + out << " bool started_receiving_writes;" << endl; out << " Address locked_read_request1;" << endl; out << " Address locked_read_request2;" << endl; out << " Address locked_read_request3;" << endl; @@ -416,6 +417,7 @@ void StateMachine::printControllerC(ostream& out, string component) out << "{ " << endl; if (strncmp(component.c_str(), "L1Cache", 7) == 0) { out << " servicing_atomic = false;" << endl; + out << " started_receiving_writes = false;" << endl; out << " locked_read_request1 = Address(-1);" << endl; out << " locked_read_request2 = Address(-1);" << endl; out << " locked_read_request3 = Address(-1);" << endl; @@ -823,6 +825,7 @@ void StateMachine::printCWakeup(ostream& out, string component) } \n \ } \n \ else if (addr != locked_read_request1) { \n \ + if (!started_receiving_writes) { \n \ if (locked_read_request2 == Address(-1)) { \n \ assert(read_counter == 1); \n \ locked_read_request2 = addr; \n \ @@ -843,6 +846,7 @@ void StateMachine::printCWakeup(ostream& out, string component) // this can happen if there are multiple optimized consequtive shifts \n \ assert(0); \n \ } \n \ + } \n \ } \n \ } \n \ else { \n \ @@ -854,6 +858,7 @@ void StateMachine::printCWakeup(ostream& out, string component) locked_read_request3 = Address(-1); \n \ locked_read_request4 = Address(-1); \n \ servicing_atomic = false; \n \ + started_receiving_writes = false; \n \ read_counter = 0; \n \ } \n \ } \n \ @@ -927,9 +932,11 @@ void StateMachine::printCWakeup(ostream& out, string component) out << "void " << component << "_Controller::clear_atomic()" << endl; out << "{" << endl; out << " assert(servicing_atomic); " << endl; + out << " started_receiving_writes = true; " << endl; out << " read_counter--; " << endl; out << " if (read_counter == 0) { " << endl; out << " servicing_atomic = false; " << endl; + out << " started_receiving_writes = false; " << endl; out << " locked_read_request1 = Address(-1); " << endl; out << " locked_read_request2 = Address(-1); " << endl; out << " locked_read_request3 = Address(-1); " << endl; |