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| author | Nuwan Jayasena <Nuwan.Jayasena@amd.com> | 2012-07-10 22:51:53 -0700 |
|---|---|---|
| committer | Nuwan Jayasena <Nuwan.Jayasena@amd.com> | 2012-07-10 22:51:53 -0700 |
| commit | 1740c4c448a65dee8b27dcdcdccdc1a6e8b4d6b6 (patch) | |
| tree | f804e0cbaae1e2bf7b0037e1b88851c2b64dfd60 /src/mem/slicc/symbols/StateMachine.py | |
| parent | 4a52a6ea2d84933a1ac8418fe2ba9222832a690d (diff) | |
| download | gem5-1740c4c448a65dee8b27dcdcdccdc1a6e8b4d6b6.tar.xz | |
ruby: memory controllers now inherit from an abstract "MemoryControl" class
Diffstat (limited to 'src/mem/slicc/symbols/StateMachine.py')
| -rw-r--r-- | src/mem/slicc/symbols/StateMachine.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 41348ba6d..8f4676c42 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -39,7 +39,7 @@ python_class_map = {"int": "Int", "WireBuffer": "RubyWireBuffer", "Sequencer": "RubySequencer", "DirectoryMemory": "RubyDirectoryMemory", - "MemoryControl": "RubyMemoryControl", + "MemoryControl": "MemoryControl", "DMASequencer": "DMASequencer" } |