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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:44 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:44 -0500
commit8114c7ff2c19540bb9147a4b97fe86bcb7f9cfde (patch)
treea1d22b063df1e55ba59b6aa9f80f7ba03bd4306d /src/mem/slicc/symbols/StateMachine.py
parent85506f1c2107cab1760ba915cf55d9e447d0625c (diff)
downloadgem5-8114c7ff2c19540bb9147a4b97fe86bcb7f9cfde.tar.xz
ruby: slicc: remove a stray line in StateMachine.py
Diffstat (limited to 'src/mem/slicc/symbols/StateMachine.py')
-rw-r--r--src/mem/slicc/symbols/StateMachine.py2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index e22c53fe8..3dce3c3f2 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -1213,8 +1213,6 @@ TransitionResult result =
else:
code('doTransitionWorker(event, state, next_state, addr);')
- port_to_buf_map, in_msg_bufs, msg_bufs = self.getBufferMaps(ident)
-
code('''
if (result == TransitionResult_Valid) {