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| author | Matteo Andreozzi <matteo.andreozzi@arm.com> | 2018-05-10 21:59:08 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-07 13:16:20 +0000 |
| commit | aa103566d6413bfdbfab7177734f0894a751a856 (patch) | |
| tree | b07a709b23ca9028e3e8ac4ca0628749d7740fcc /src/mem/slicc/symbols/Transition.py | |
| parent | 66f80b5a731e2fac5d9e4f841804d87a1267b76a (diff) | |
| download | gem5-aa103566d6413bfdbfab7177734f0894a751a856.tar.xz | |
mem: Add a simple QoS-aware Memory Controller
This patch implements QoSMemorySink: a simple generic QoS-aware memory
controller which inherits from QoS::MemCtrl.
Change-Id: I537a4e2d4cb8f54fa0002eb088b2c6957afb9973
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11971
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Matthew Poremba <porembam@gmail.com>
Diffstat (limited to 'src/mem/slicc/symbols/Transition.py')
0 files changed, 0 insertions, 0 deletions