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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-14 12:04:51 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-14 12:04:51 -0500
commit91a84c5b3cfb888794ac0245c066a4724b9a0871 (patch)
tree79a8b41aff56655dbd187934d2709fdd7488c6ed /src/mem/slicc/symbols/Type.py
parent9ea5d9cad9381e05004de28ef25309ebe94c3a79 (diff)
downloadgem5-91a84c5b3cfb888794ac0245c066a4724b9a0871.tar.xz
ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system.
Diffstat (limited to 'src/mem/slicc/symbols/Type.py')
-rw-r--r--src/mem/slicc/symbols/Type.py5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 73d6f9c69..5fd63d834 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -451,6 +451,7 @@ ${{self.c_ident}}::print(ostream& out) const
if self.isMachineType:
code('#include "base/misc.hh"')
code('#include "mem/ruby/common/Address.hh"')
+ code('#include "mem/ruby/common/TypeDefines.hh"')
code('struct MachineID;')
code('''
@@ -499,7 +500,7 @@ int ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj);
for enum in self.enums.itervalues():
if enum.ident == "DMA":
code('''
-MachineID map_Address_to_DMA(const Address &addr);
+MachineID map_Address_to_DMA(const Addr &addr);
''')
code('''
@@ -750,7 +751,7 @@ ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj)
if enum.ident == "DMA":
code('''
MachineID
-map_Address_to_DMA(const Address &addr)
+map_Address_to_DMA(const Addr &addr)
{
MachineID dma = {MachineType_DMA, 0};
return dma;