diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-01-29 20:29:17 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-01-29 20:29:17 -0800 |
| commit | c6f1d959be74de55b0c90f3c961314791342d03e (patch) | |
| tree | d0ef0777894828291a6ced188c8bcae323cea442 /src/mem/slicc/symbols/Type.py | |
| parent | 98c94cfe3ce83634f3bad79ca18263f42e36ca6a (diff) | |
| download | gem5-c6f1d959be74de55b0c90f3c961314791342d03e.tar.xz | |
ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
Diffstat (limited to 'src/mem/slicc/symbols/Type.py')
| -rw-r--r-- | src/mem/slicc/symbols/Type.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py index bafc6ea9e..fc45c59df 100644 --- a/src/mem/slicc/symbols/Type.py +++ b/src/mem/slicc/symbols/Type.py @@ -478,7 +478,6 @@ ostream& operator<<(ostream& out, const ${{self.c_ident}}& obj); ''') if self.isMachineType: - code('#include "mem/protocol/ControllerFactory.hh"') for enum in self.enums.itervalues(): code('#include "mem/protocol/${{enum.ident}}_Controller.hh"') |