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authorNikos Nikoleris <nikos.nikoleris@arm.com>2017-03-13 18:19:08 +0000
committerNikos Nikoleris <nikos.nikoleris@arm.com>2017-06-13 15:52:32 +0000
commit12db50c89584938839e035da47d206250cbfd7c2 (patch)
tree831a4151b29cdc14958b8dab2cce97fc3136d7b6 /src/mem/slicc/symbols
parentdd3fc1f996679f4cfd29f980d43a0652542e6d9b (diff)
downloadgem5-12db50c89584938839e035da47d206250cbfd7c2.tar.xz
ruby: Add support for address ranges in the directory
Previously the directory covered a flat address range that always started from address 0. This change adds a vector of address ranges with interleaving and hashing that each directory keeps track of and the necessary flexibility to support systems with non continuous memory ranges. Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2903 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/mem/slicc/symbols')
-rw-r--r--src/mem/slicc/symbols/Type.py15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index bd92e20c9..e62758305 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -459,6 +459,7 @@ out << "${{dm.ident}} = " << printAddress(m_${{dm.ident}}) << " ";''')
code('#include "mem/protocol/AccessPermission.hh"')
if self.isMachineType:
+ code('#include <functional>')
code('#include "base/misc.hh"')
code('#include "mem/ruby/common/Address.hh"')
code('#include "mem/ruby/common/TypeDefines.hh"')
@@ -498,6 +499,20 @@ std::string ${{self.c_ident}}_to_string(const ${{self.c_ident}}& obj);
${{self.c_ident}} &operator++(${{self.c_ident}} &e);
''')
+ if self.isMachineType:
+ code('''
+
+// define a hash function for the MachineType class
+namespace std {
+template<>
+struct hash<MachineType> {
+ std::size_t operator()(const MachineType &mtype) const {
+ return hash<size_t>()(static_cast<size_t>(mtype));
+ }
+};
+}
+
+''')
# MachineType hack used to set the base component id for each Machine
if self.isMachineType:
code('''