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author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-23 16:41:59 -0800 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-23 16:41:59 -0800 |
commit | 12a05c23b7d351afee4b0c531021d8fb8ea5f57d (patch) | |
tree | 99a18647ecf642166068187915f2816a1007567d /src/mem/slicc/symbols | |
parent | 7842e955193c3fba850201acc45001306fe2ff9b (diff) | |
download | gem5-12a05c23b7d351afee4b0c531021d8fb8ea5f57d.tar.xz |
ruby: automate permission setting
This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.
--HG--
rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py
rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
Diffstat (limited to 'src/mem/slicc/symbols')
-rw-r--r-- | src/mem/slicc/symbols/StateMachine.py | 13 | ||||
-rw-r--r-- | src/mem/slicc/symbols/Type.py | 40 |
2 files changed, 53 insertions, 0 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 1251196c9..3c5f860ea 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -347,6 +347,8 @@ static int m_num_controllers; // Set and Reset for cache_entry variable void set_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, AbstractCacheEntry* m_new_cache_entry); void unset_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr); +// Set permissions for the cache_entry +void set_permission(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, AccessPermission perm); ''') if self.TBEType != None: @@ -850,6 +852,15 @@ $c_ident::unset_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr) { m_cache_entry_ptr = 0; } + +void +$c_ident::set_permission(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, + AccessPermission perm) +{ + if (m_cache_entry_ptr != NULL) { + m_cache_entry_ptr->changePermission(perm); + } +} ''') if self.TBEType != None: @@ -1090,10 +1101,12 @@ ${ident}_Controller::doTransition(${ident}_Event event, ''') if self.TBEType != None and self.EntryType != None: code('${ident}_setState(m_tbe_ptr, m_cache_entry_ptr, addr, next_state);') + code('set_permission(m_cache_entry_ptr, ${ident}_State_to_permission(next_state));') elif self.TBEType != None: code('${ident}_setState(m_tbe_ptr, addr, next_state);') elif self.EntryType != None: code('${ident}_setState(m_cache_entry_ptr, addr, next_state);') + code('set_permission(m_cache_entry_ptr, ${ident}_State_to_permission(next_state));') else: code('${ident}_setState(addr, next_state);') diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py index e521d544f..da9ecba3a 100644 --- a/src/mem/slicc/symbols/Type.py +++ b/src/mem/slicc/symbols/Type.py @@ -100,6 +100,9 @@ class Type(Symbol): self.isMachineType = (ident == "MachineType") + self.isStateDecl = ("state_decl" in self) + self.statePermPairs = [] + self.data_members = orderdict() # Methods @@ -158,6 +161,9 @@ class Type(Symbol): def methodIdAbstract(self, name, param_type_vec): return '_'.join([name] + [ pt.abstract_ident for pt in param_type_vec ]) + def statePermPairAdd(self, state_name, perm_name): + self.statePermPairs.append([state_name, perm_name]) + def methodAdd(self, name, return_type, param_type_vec): ident = self.methodId(name, param_type_vec) if ident in self.methods: @@ -446,6 +452,11 @@ ${{self.c_ident}}::print(ostream& out) const #include <string> #include "mem/ruby/common/Global.hh" +''') + if self.isStateDecl: + code('#include "mem/protocol/AccessPermission.hh"') + + code(''' // Class definition /** \\enum ${{self.c_ident}} @@ -491,6 +502,14 @@ int ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj); for enum in self.enums.itervalues(): code('#define MACHINETYPE_${{enum.ident}} 1') + if self.isStateDecl: + code(''' + +// Code to convert the current state to an access permission +AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj); + +''') + # Trailer code(''' std::ostream& operator<<(std::ostream& out, const ${{self.c_ident}}& obj); @@ -519,6 +538,27 @@ using namespace std; ''') + if self.isStateDecl: + code(''' +// Code to convert the current state to an access permission +AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj) +{ + switch(obj) { +''') + # For each case + code.indent() + for statePerm in self.statePermPairs: + code(' case ${{self.c_ident}}_${{statePerm[0]}}:') + code(' return AccessPermission_${{statePerm[1]}};') + code.dedent() + code (''' + default: + panic("Unknown state access permission converstion for ${{self.c_ident}}"); + } +} + +''') + if self.isMachineType: for enum in self.enums.itervalues(): code('#include "mem/protocol/${{enum.ident}}_Controller.hh"') |