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authorNilay Vaish <nilay@cs.wisc.edu>2011-10-28 13:00:35 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2011-10-28 13:00:35 -0500
commitcbaebb3b5ebe709689f481ad395034335bea2152 (patch)
tree075d77442e387879ff316fced83d08ea32f3c105 /src/mem/slicc/symbols
parentf2bfef90c4441ea77025ebb3de398f9d66bbffdf (diff)
downloadgem5-cbaebb3b5ebe709689f481ad395034335bea2152.tar.xz
Ruby: Reorganize mapping of components
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for mapping MachineType to GenericMachineType. These '#define's are being eliminated and the code will now be generated by SLICC instead. Also are being eliminated some of the unused functions from RubySlicc_ComponentMapping.sm.
Diffstat (limited to 'src/mem/slicc/symbols')
-rw-r--r--src/mem/slicc/symbols/Type.py53
1 files changed, 52 insertions, 1 deletions
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index b41ecc00f..36be8c25a 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -444,6 +444,13 @@ ${{self.c_ident}}::print(ostream& out) const
if self.isStateDecl:
code('#include "mem/protocol/AccessPermission.hh"')
+ if self.isMachineType:
+ code('#include "base/misc.hh"')
+ code('#include "mem/protocol/GenericMachineType.hh"')
+ code('#include "mem/ruby/common/Address.hh"')
+ code('#include "mem/ruby/system/NodeID.hh"')
+ code('struct MachineID;')
+
code('''
// Class definition
@@ -488,7 +495,29 @@ int ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj);
''')
for enum in self.enums.itervalues():
- code('#define MACHINETYPE_${{enum.ident}} 1')
+ if enum.ident == "DMA":
+ code('''
+MachineID map_Address_to_DMA(const Address &addr);
+''')
+ code('''
+
+MachineID get${{enum.ident}}MachineID(NodeID RubyNode);
+''')
+
+ code('''
+inline GenericMachineType
+ConvertMachToGenericMach(MachineType machType)
+{
+''')
+ for enum in self.enums.itervalues():
+ code('''
+ if (machType == MachineType_${{enum.ident}})
+ return GenericMachineType_${{enum.ident}};
+''')
+ code('''
+ panic("cannot convert to a GenericMachineType");
+}
+''')
if self.isStateDecl:
code('''
@@ -550,6 +579,7 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj)
if self.isMachineType:
for enum in self.enums.itervalues():
code('#include "mem/protocol/${{enum.ident}}_Controller.hh"')
+ code('#include "mem/ruby/system/MachineID.hh"')
code('''
// Code for output operator
@@ -723,6 +753,27 @@ ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj)
}
''')
+ for enum in self.enums.itervalues():
+ if enum.ident == "DMA":
+ code('''
+MachineID
+map_Address_to_DMA(const Address &addr)
+{
+ MachineID dma = {MachineType_DMA, 0};
+ return dma;
+}
+''')
+
+ code('''
+
+MachineID
+get${{enum.ident}}MachineID(NodeID RubyNode)
+{
+ MachineID mach = {MachineType_${{enum.ident}}, RubyNode};
+ return mach;
+}
+''')
+
# Write the file
code.write(path, "%s.cc" % self.c_ident)