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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-22 15:53:24 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-22 15:53:24 -0500 |
commit | 870d54578897a099128d446ddc5801e556f93056 (patch) | |
tree | 024f5dbcdd0b7e686f13149cf3c91dd807e41ff3 /src/mem/slicc/symbols | |
parent | 8573a69d8f7bf7b3f074e3e0ac64994801c551be (diff) | |
download | gem5-870d54578897a099128d446ddc5801e556f93056.tar.xz |
slicc: remove check if the L1Cache has a sequencer
Diffstat (limited to 'src/mem/slicc/symbols')
-rw-r--r-- | src/mem/slicc/symbols/StateMachine.py | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 3618563fd..4a33d78ba 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -482,19 +482,8 @@ $c_ident::$c_ident(const Params *p) # For the l1 cache controller, add the special atomic support which # includes passing the sequencer a pointer to the controller. # - if self.ident == "L1Cache": - if not sequencers: - self.error("The L1Cache controller must include the sequencer " \ - "configuration parameter") - - for seq in sequencers: - code(''' -m_${{seq}}_ptr->setController(this); - ''') - - else: - for seq in sequencers: - code(''' + for seq in sequencers: + code(''' m_${{seq}}_ptr->setController(this); ''') |