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| author | Lisa Hsu <Lisa.Hsu@amd.com> | 2011-03-31 17:17:57 -0700 |
|---|---|---|
| committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2011-03-31 17:17:57 -0700 |
| commit | 322b9ca2c5b0465db7086abdc6eadca061932575 (patch) | |
| tree | b14837962707de7b90b95c0b0a7b09ffa1988847 /src/mem/slicc | |
| parent | 06fcaf9104cefe5a2c0062b9357dae46bfd9992a (diff) | |
| download | gem5-322b9ca2c5b0465db7086abdc6eadca061932575.tar.xz | |
Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between controllers where you don't
want messages to actually go through the Network, because requests/responses can
always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered)
because you are, after all, going through a network with contention. For systems where you model
multiple controllers that are very tightly coupled and do not actually go through a network,
it is a pain to have to write a coherence protocol to account for mixed up request/response orderings
despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real
MessageBuffers when messages do in fact go over a network.
Diffstat (limited to 'src/mem/slicc')
| -rw-r--r-- | src/mem/slicc/symbols/StateMachine.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 71b786616..90b7bfbd8 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -36,6 +36,7 @@ python_class_map = {"int": "Int", "std::string": "String", "bool": "Bool", "CacheMemory": "RubyCache", + "WireBuffer": "RubyWireBuffer", "Sequencer": "RubySequencer", "DirectoryMemory": "RubyDirectoryMemory", "MemoryControl": "RubyMemoryControl", |