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authorBrad Beckmann <Brad.Beckmann@amd.com>2012-07-10 22:51:54 -0700
committerBrad Beckmann <Brad.Beckmann@amd.com>2012-07-10 22:51:54 -0700
commit86d6b788f6d7b523c750ffb64d6d8920ec741c49 (patch)
tree2d6be00e66218b39bae31a27380a47283f70c097 /src/mem/slicc
parent467093ebf238a1954e00576daf14a9f246b51e79 (diff)
downloadgem5-86d6b788f6d7b523c750ffb64d6d8920ec741c49.tar.xz
ruby: banked cache array resource model
This patch models a cache as separate tag and data arrays. The patch exposes the banked array as another resource that is checked by SLICC before a transition is allowed to execute. This is similar to how TBE entries and slots in output ports are modeled.
Diffstat (limited to 'src/mem/slicc')
-rw-r--r--src/mem/slicc/symbols/StateMachine.py8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 230eb1b22..39f3a4b43 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -1238,6 +1238,14 @@ if (!%s.areNSlotsAvailable(%s))
''' % (key.code, val)
case_sorter.append(val)
+ # Check all of the request_types for resource constraints
+ for request_type in request_types:
+ val = '''
+if (!checkResourceAvailable(%s_RequestType_%s, addr)) {
+ return TransitionResult_ResourceStall;
+}
+''' % (self.ident, request_type.ident)
+ case_sorter.append(val)
# Emit the code sequences in a sorted order. This makes the
# output deterministic (without this the output order can vary