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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-03-21 21:22:21 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-03-21 21:22:21 -0700 |
| commit | 92cfd1cac7f6f2d0abf64808f08f063cd0db1263 (patch) | |
| tree | a69a2964f7342083cd8aaca5ed32df207a1edea8 /src/mem/slicc | |
| parent | b5e4c3cbf2de32e18029b44b16b307a773b6ecf7 (diff) | |
| download | gem5-92cfd1cac7f6f2d0abf64808f08f063cd0db1263.tar.xz | |
ruby: Ruby support for sparse memory
The patch includes direct support for the MI example protocol.
Diffstat (limited to 'src/mem/slicc')
| -rw-r--r-- | src/mem/slicc/symbols/StateMachine.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 6614c7bd0..0c66ddab4 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -651,6 +651,7 @@ $c_ident::printStats(ostream& out) const # for param in self.config_parameters: if param.type_ast.type.ident == "CacheMemory" or \ + param.type_ast.type.ident == "DirectoryMemory" or \ param.type_ast.type.ident == "MemoryControl": assert(param.pointer) code(' m_${{param.ident}}_ptr->printStats(out);') |