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authorNilay Vaish <nilay@cs.wisc.edu>2014-01-04 00:03:34 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-01-04 00:03:34 -0600
commit4070b00875a5fcc3cde61ff0b32fbee882998189 (patch)
tree245f49626f3abf0c378397025638adc7afaee9b5 /src/mem/slicc
parentbb6d7d402b5cc610ed879e9e7ecb251e353149e6 (diff)
downloadgem5-4070b00875a5fcc3cde61ff0b32fbee882998189.tar.xz
ruby: add a three level MESI protocol.
The first two levels (L0, L1) are private to the core, the third level (L2)is possibly shared. The protocol supports clustered designs. For example, one can have two sets of two cores. Each core has an L0 and L1 cache. There are two L2 controllers where each set accesses only one of the L2 controllers.
Diffstat (limited to 'src/mem/slicc')
-rw-r--r--src/mem/slicc/symbols/StateMachine.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index b969d79a3..1106dcadc 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -543,7 +543,7 @@ void
$c_ident::init()
{
MachineType machine_type = string_to_MachineType("${{var.machine.ident}}");
- int base = MachineType_base_number(machine_type);
+ int base M5_VAR_USED = MachineType_base_number(machine_type);
m_machineID.type = MachineType_${ident};
m_machineID.num = m_version;