mem-ruby: Adding a new slicc statement - to not evict locked cachelines

Ruby caches block incoming ports with messages on a locked
address to make sure the line would not be replaced by others.
But they do not check the lock upon capacity/conflict misses.

This change adds a new slicc statement "check_on_cache_probe" which takes
two arguments (mandatoryQueue for the controller, and the line subject
to eviction - i.e. address returned by cacheProbe).
If the line is locked, incoming message is delayed for 1 cycle and the
controller skips this request (i.e. does not trigger an event).

Coherence protocols should be updated accordingly. One use case for MESI
Two Level will be added in a separate change.

Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: I79ca2d45518de7a4e382b520a11f8e221b0cb803
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16808
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

3 files changed, 59 insertions, 0 deletions

diff --git a/src/mem/slicc/ast/CheckProbeStatementAST.py b/src/mem/slicc/ast/CheckProbeStatementAST.py
new file mode 100644
index 000000000..53454635a
--- /dev/null
+++ b/src/mem/slicc/ast/CheckProbeStatementAST.py
@@ -0,0 +1,53 @@
+# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+# Copyright (c) 2009 The Hewlett-Packard Development Company
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class CheckProbeStatementAST(StatementAST):
+    def __init__(self, slicc, in_port, address):
+        super(StatementAST, self).__init__(slicc)
+        self.in_port = in_port
+        self.address = address
+
+    def __repr__(self):
+        return "[CheckProbeStatementAst: %r]" % self.in_port
+
+    def generate(self, code, return_type):
+        self.in_port.assertType("InPort")
+        self.address.assertType("Addr")
+
+        in_port_code = self.in_port.var.code
+        address_code = self.address.var.code
+        code('''
+    if (m_is_blocking &&
+        (m_block_map.count($address_code) == 1) &&
+        (m_block_map[$address_code] == &$in_port_code)) {
+            $in_port_code.delayHead(clockEdge(), cyclesToTicks(Cycles(1)));
+            continue;
+        }
+        ''')
diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py
index c5c616a55..e3169e8b5 100644
--- a/src/mem/slicc/ast/__init__.py
+++ b/src/mem/slicc/ast/__init__.py
@@ -70,3 +70,4 @@ from slicc.ast.TypeFieldAST import *
 from slicc.ast.TypeFieldEnumAST import *
 from slicc.ast.TypeFieldStateAST import *
 from slicc.ast.VarExprAST import *
+from slicc.ast.CheckProbeStatementAST import *
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 5c2b212a2..1df5b7782 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -113,6 +113,7 @@ class SLICC(Grammar):
         'check_allocate' : 'CHECK_ALLOCATE',
         'check_next_cycle' : 'CHECK_NEXT_CYCLE',
         'check_stop_slots' : 'CHECK_STOP_SLOTS',
+        'check_on_cache_probe' : 'CHECK_PROBE',
         'static_cast' : 'STATIC_CAST',
         'if' : 'IF',
         'is_valid' : 'IS_VALID',
@@ -605,6 +606,10 @@ class SLICC(Grammar):
         "statement : CHECK_STOP_SLOTS '(' var ',' STRING ',' STRING ')' SEMI"
         p[0] = ast.CheckStopStatementAST(self, p[3], p[5], p[7])
 
+    def p_statement__check_probe(self, p):
+        "statement : CHECK_PROBE '(' var ',' var ')' SEMI"
+        p[0] = ast.CheckProbeStatementAST(self, p[3], p[5])
+
     def p_statement__return(self, p):
         "statement : RETURN expr SEMI"
         p[0] = ast.ReturnStatementAST(self, p[2])