Use fixPacket function everywhere.

Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
    Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Use fix Packet function
src/mem/packet.cc:
    Fix an assert that was checking the wrong thing
src/mem/tport.cc:
    Properly detect if we need to do the access to the functional device

--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e

1 files changed, 8 insertions, 6 deletions

diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 2d8e7dba4..479dca1ad 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -33,12 +33,13 @@
 void
 SimpleTimingPort::recvFunctional(Packet *pkt)
 {
-    //First check queued events
-    std::list<Packet *>::iterator i = transmitList.begin();
-    std::list<Packet *>::iterator end = transmitList.end();
-    bool cont = true;
+    std::list<Packet *>::iterator i;
+    std::list<Packet *>::iterator end;
 
-    while (i != end && cont) {
+     //First check queued events
+    i = transmitList.begin();
+    end = transmitList.end();
+    while (i != end) {
         Packet * target = *i;
         // If the target contains data, and it overlaps the
         // probed request, need to update data
@@ -46,8 +47,9 @@ SimpleTimingPort::recvFunctional(Packet *pkt)
             fixPacket(pkt, target);
 
     }
+
     //Then just do an atomic access and throw away the returned latency
-    if (cont)
+    if (pkt->result != Packet::Success)
         recvAtomic(pkt);
 }