Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request.

Still need to rework upgrades into this system, but works for now.

src/mem/cache/base_cache.cc:
    Re order code to be more readable
src/mem/cache/base_cache.hh:
    Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
    Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
    Demorgans to make it easier to understand
src/mem/tport.cc:
    Delete writebacks

--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e

1 files changed, 7 insertions, 0 deletions

diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 21907c0ca..2d8e7dba4 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -66,6 +66,13 @@ SimpleTimingPort::recvTiming(Packet *pkt)
         pkt->makeTimingResponse();
         sendTimingLater(pkt, latency);
     }
+    else {
+        if (pkt->cmd != Packet::UpgradeReq)
+        {
+            delete pkt->req;
+            delete pkt;
+        }
+    }
     return true;
 }