diff options
author | Wendy Elsasser <wendy.elsasser@arm.com> | 2014-09-20 17:18:21 -0400 |
---|---|---|
committer | Wendy Elsasser <wendy.elsasser@arm.com> | 2014-09-20 17:18:21 -0400 |
commit | bf238470726b4cc5c0b34fcb349d767726fe53bc (patch) | |
tree | f04c382caae938fe688affbafdbbfdb803a307fd /src/mem/tport.hh | |
parent | b6ecfe918364ce4b7df0f95590b483100bbfcba9 (diff) | |
download | gem5-bf238470726b4cc5c0b34fcb349d767726fe53bc.tar.xz |
mem: Add DDR4 bank group timing
Added the following parameter to the DRAMCtrl class:
- bank_groups_per_rank
This defaults to 1. For the DDR4 case, the default is overridden to indicate
bank group architecture, with multiple bank groups per rank.
Added the following delays to the DRAMCtrl class:
- tCCD_L : CAS-to-CAS, same bank group delay
- tRRD_L : RAS-to-RAS, same bank group delay
These parameters are only applied when bank group timing is enabled. Bank
group timing is currently enabled only for DDR4 memories.
For all other memories, these delays will default to '0 ns'
In the DRAM controller model, applied the bank group timing to the per bank
parameters actAllowedAt and colAllowedAt.
The actAllowedAt will be updated based on bank group when an ACT is issued.
The colAllowedAt will be updated based on bank group when a RD/WR burst is
issued.
At the moment no modifications are made to the scheduling.
Diffstat (limited to 'src/mem/tport.hh')
0 files changed, 0 insertions, 0 deletions