diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-30 13:34:16 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-30 13:34:16 -0700 |
| commit | 6babda7123be5e69db137e77589d88c768c19345 (patch) | |
| tree | 6317fb3559996a36602e3d66b5e0b5ea63a2a5f8 /src/mem/tport.hh | |
| parent | 6ab53415efe3e06c06589a8a6ef38185ff6f94b7 (diff) | |
| download | gem5-6babda7123be5e69db137e77589d88c768c19345.tar.xz | |
Fix up a few statistics problems.
Stats pretty much line up with old code, except:
- bug in old code included L1 latency in L2 miss time, making it too high
- UniCoherence did cache-to-cache transfers even from non-owner caches,
so occasionally the icache would get a block from the dcache not the L2
- L2 can now receive ReadExReq from L1 since L1s have coherence
--HG--
extra : convert_revision : 5052c1a1767b5a662f30a88f16012165a73b791c
Diffstat (limited to 'src/mem/tport.hh')
| -rw-r--r-- | src/mem/tport.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/tport.hh b/src/mem/tport.hh index bfed29f34..bc9da6c44 100644 --- a/src/mem/tport.hh +++ b/src/mem/tport.hh @@ -105,7 +105,7 @@ class SimpleTimingPort : public Port bool deferredPacketReady() { return !transmitList.empty() && transmitList.front().tick <= curTick; } - Tick deferredPacketReadyTick() + Tick deferredPacketReadyTime() { return transmitList.empty() ? MaxTick : transmitList.front().tick; } void schedSendEvent(Tick when) |