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author | Gabe Black <gabeblack@google.com> | 2019-04-22 19:45:10 -0700 |
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committer | Gabe Black <gabeblack@google.com> | 2019-04-28 01:19:40 +0000 |
commit | cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 (patch) | |
tree | 893cea35432466600b55a2e4434ed61ba1e28f69 /src/mem/tport.hh | |
parent | 3cfff8574a19536e2b3d057b43b59fcf35932c81 (diff) | |
download | gem5-cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9.tar.xz |
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/mem/tport.hh')
-rw-r--r-- | src/mem/tport.hh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/tport.hh b/src/mem/tport.hh index d7e4bbc74..d62b1405d 100644 --- a/src/mem/tport.hh +++ b/src/mem/tport.hh @@ -52,6 +52,8 @@ #include "mem/qport.hh" +class SimObject; + /** * The simple timing port uses a queued port to implement * recvFunctional and recvTimingReq through recvAtomic. It is always a @@ -99,7 +101,7 @@ class SimpleTimingPort : public QueuedSlavePort * @param name port name * @param owner structural owner */ - SimpleTimingPort(const std::string& name, MemObject* owner); + SimpleTimingPort(const std::string& name, SimObject* owner); virtual ~SimpleTimingPort() { } |