arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.

--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc

10 files changed, 18 insertions, 25 deletions

diff --git a/src/mem/SConscript b/src/mem/SConscript
index ca89418b5..02d0aee73 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -36,11 +36,15 @@ if env['HAVE_PROTOBUF']:
     SimObject('CommMonitor.py')
     Source('comm_monitor.cc')
 
+SimObject('AbstractMemory.py')
 SimObject('AddrMapper.py')
 SimObject('Bridge.py')
 SimObject('Bus.py')
 SimObject('MemObject.py')
+SimObject('SimpleMemory.py')
+SimObject('SimpleDRAM.py')
 
+Source('abstract_mem.cc')
 Source('addr_mapper.cc')
 Source('bridge.cc')
 Source('bus.cc')
@@ -53,18 +57,14 @@ Source('port.cc')
 Source('packet_queue.cc')
 Source('tport.cc')
 Source('port_proxy.cc')
-Source('fs_translating_port_proxy.cc')
-Source('se_translating_port_proxy.cc')
+Source('simple_mem.cc')
+Source('physical.cc')
+Source('simple_dram.cc')
 
-if env['TARGET_ISA'] != 'no':
-    SimObject('AbstractMemory.py')
-    SimObject('SimpleMemory.py')
-    SimObject('SimpleDRAM.py')
-    Source('abstract_mem.cc')
-    Source('simple_mem.cc')
+if env['TARGET_ISA'] != 'null':
+    Source('fs_translating_port_proxy.cc')
+    Source('se_translating_port_proxy.cc')
     Source('page_table.cc')
-    Source('physical.cc')
-    Source('simple_dram.cc')
 
 DebugFlag('BaseBus')
 DebugFlag('BusAddrRanges')
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index 8323602d2..a4fbe04c0 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -30,9 +30,6 @@
 
 Import('*')
 
-if env['TARGET_ISA'] == 'no':
-    Return()
-
 SimObject('BaseCache.py')
 
 Source('base.cc')
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 03b4d5dc1..af324527f 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -45,8 +45,6 @@
  * Definition of BaseCache functions.
  */
 
-#include "cpu/base.hh"
-#include "cpu/smt.hh"
 #include "debug/Cache.hh"
 #include "debug/Drain.hh"
 #include "mem/cache/tags/fa_lru.hh"
diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript
index 2310940c1..61291f715 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -30,8 +30,6 @@
 
 Import('*')
 
-if env['TARGET_ISA'] == 'no':
-    Return()
 SimObject('Prefetcher.py')
 
 Source('base.cc')
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index de835c1d0..dca8d3bd8 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -30,9 +30,6 @@
 
 Import('*')
 
-if env['TARGET_ISA'] == 'no':
-    Return()
-
 SimObject('Tags.py')
 
 Source('base.cc')
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index d9909f5de..947bd05de 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -46,6 +46,7 @@
  * Definitions of BaseTags.
  */
 
+#include "config/the_isa.hh"
 #include "cpu/smt.hh" //maxThreadsPerCPU
 #include "mem/cache/tags/base.hh"
 #include "mem/cache/base.hh"
diff --git a/src/mem/fs_translating_port_proxy.cc b/src/mem/fs_translating_port_proxy.cc
index 8fb9b91ef..52e8b49d8 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -46,6 +46,7 @@
  * Port object definitions.
  */
 
+#include "arch/vtophys.hh"
 #include "base/chunk_generator.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/mem/fs_translating_port_proxy.hh b/src/mem/fs_translating_port_proxy.hh
index 2a9223050..c8f099d2c 100644
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -59,9 +59,10 @@
 #ifndef __MEM_FS_PORT_PROXY_HH__
 #define __MEM_FS_PORT_PROXY_HH__
 
-#include "arch/vtophys.hh"
 #include "mem/port_proxy.hh"
 
+class ThreadContext;
+
 /**
  * A TranslatingPortProxy in FS mode translates a virtual address to a
  * physical address and then calls the read/write functions of the
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index f1e01c385..1213daafa 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -60,7 +60,7 @@
 #define __MEM_PORT_PROXY_HH__
 
 #include "config/the_isa.hh"
-#if THE_ISA != NO_ISA
+#if THE_ISA != NULL_ISA
     #include "arch/isa_traits.hh"
 #endif
 
@@ -127,7 +127,7 @@ class PortProxy
     template <typename T>
     void write(Addr address, T data) const;
 
-#if THE_ISA != NO_ISA
+#if THE_ISA != NULL_ISA
     /**
      * Read sizeof(T) bytes from address and return as object T.
      * Performs Guest to Host endianness transform.
@@ -161,7 +161,7 @@ PortProxy::write(Addr address, T data) const
     writeBlob(address, (uint8_t*)&data, sizeof(T));
 }
 
-#if THE_ISA != NO_ISA
+#if THE_ISA != NULL_ISA
 template <typename T>
 T
 PortProxy::readGtoH(Addr address) const
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index 086c2f764..b655caa7d 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -37,7 +37,7 @@ import SCons
 
 Import('*')
 
-if env['TARGET_ISA'] == 'no':
+if env['TARGET_ISA'] == 'null':
     Return()
 
 if env['PROTOCOL'] == 'None':