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author | Iru Cai <mytbk920423@gmail.com> | 2019-05-11 21:41:14 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-11 21:41:14 +0800 |
commit | 2b62fec3590024a7ce82ef5d4647397d37ed37eb (patch) | |
tree | 8f4a6d9bed9d5006f3d5d9ac94b1b6b5fa8d5578 /src/mem | |
parent | 3b26d5f86c9a427e6ab9b9fa688b76ab2034a0d2 (diff) | |
download | gem5-2b62fec3590024a7ce82ef5d4647397d37ed37eb.tar.xz |
try not expose if L1 hitis-ift-cachehit
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/protocol/MESI_Two_Level-L1cache.sm | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index 846af7da5..f5feb7e23 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -1323,6 +1323,7 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") transition({S,E,M}, SpecLoad) { h_spec_load_hit; + uu_profileDataHit; k_popMandatoryQueue; } |