diff options
author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-17 16:47:22 -0400 |
---|---|---|
committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-17 16:47:22 -0400 |
commit | 4fff6d460311d77e0056a546df41366d5a3b4604 (patch) | |
tree | e53419f2e4c6c38ff874e144d22fabeb9f637e6d /src/mem | |
parent | 6e8bfa4e63cd09b065b77166577104c06636b6f3 (diff) | |
download | gem5-4fff6d460311d77e0056a546df41366d5a3b4604.tar.xz |
Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request.
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/cache/base_cache.cc | 18 | ||||
-rw-r--r-- | src/mem/cache/base_cache.hh | 14 | ||||
-rw-r--r-- | src/mem/cache/cache_impl.hh | 12 | ||||
-rw-r--r-- | src/mem/cache/miss/mshr_queue.cc | 2 | ||||
-rw-r--r-- | src/mem/tport.cc | 7 |
5 files changed, 43 insertions, 10 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 30c996d4f..6250b72d4 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -179,16 +179,23 @@ BaseCache::CachePort::recvRetry() return; } pkt = cache->getPacket(); - MSHR* mshr = (MSHR*)pkt->senderState; + MSHR* mshr = (MSHR*) pkt->senderState; //Copy the packet, it may be modified/destroyed elsewhere Packet * copyPkt = new Packet(*pkt); copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>()); mshr->pkt = copyPkt; + bool success = sendTiming(pkt); DPRINTF(Cache, "Address %x was %s in sending the timing request\n", pkt->getAddr(), success ? "succesful" : "unsuccesful"); - cache->sendResult(pkt, mshr, success); + waitingOnRetry = !success; + if (waitingOnRetry) { + DPRINTF(CachePort, "%s now waiting on a retry\n", name()); + } + + cache->sendResult(pkt, mshr, success); + if (success && cache->doMasterRequest()) { DPRINTF(CachePort, "%s has more requests\n", name()); @@ -301,10 +308,13 @@ BaseCache::CacheEvent::process() bool success = cachePort->sendTiming(pkt); DPRINTF(Cache, "Address %x was %s in sending the timing request\n", pkt->getAddr(), success ? "succesful" : "unsuccesful"); - cachePort->cache->sendResult(pkt, mshr, success); + cachePort->waitingOnRetry = !success; - if (cachePort->waitingOnRetry) + if (cachePort->waitingOnRetry) { DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + } + + cachePort->cache->sendResult(pkt, mshr, success); if (success && cachePort->cache->doMasterRequest()) { DPRINTF(CachePort, "%s still more MSHR requests to send\n", diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 7a9e57430..8814abb38 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -525,8 +525,11 @@ class BaseCache : public MemObject reqCpu->schedule(time); } else { - if (pkt->cmd == Packet::Writeback) delete pkt->req; - delete pkt; + if (pkt->cmd != Packet::UpgradeReq) + { + delete pkt->req; + delete pkt; + } } } @@ -545,8 +548,11 @@ class BaseCache : public MemObject reqCpu->schedule(time); } else { - if (pkt->cmd == Packet::Writeback) delete pkt->req; - delete pkt; + if (pkt->cmd != Packet::UpgradeReq) + { + delete pkt->req; + delete pkt; + } } } diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index a64ce4e09..44d7b4895 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -273,9 +273,14 @@ void Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success) { if (success && !(pkt && (pkt->flags & NACKED_LINE))) { + if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq) + && (pkt && (pkt->flags & SATISFIED))) { + //Writeback, clean up the non copy version of the packet + delete pkt; + } missQueue->markInService(mshr->pkt, mshr); //Temp Hack for UPGRADES - if (mshr->pkt->cmd == Packet::UpgradeReq) { + if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) { assert(pkt); //Upgrades need to be fixed pkt->flags &= ~CACHE_LINE_FILL; BlkType *blk = tags->findBlock(pkt); @@ -295,6 +300,11 @@ Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool pkt->flags &= ~NACKED_LINE; pkt->flags &= ~SATISFIED; pkt->flags &= ~SNOOP_COMMIT; + +//Rmove copy from mshr + delete mshr->pkt; + mshr->pkt = pkt; + missQueue->restoreOrigCmd(pkt); } } diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index 1876a8987..9d2a692cf 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -213,7 +213,7 @@ void MSHRQueue::markInService(MSHR* mshr) { //assert(mshr == pendingList.front()); - if (!(mshr->pkt->needsResponse() || mshr->pkt->cmd == Packet::UpgradeReq)) { + if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq)) { assert(mshr->getNumTargets() == 0); if ((mshr->pkt->flags & SATISFIED) && (mshr->pkt->cmd == Packet::Writeback)) { //Writeback hit, so delete it diff --git a/src/mem/tport.cc b/src/mem/tport.cc index 21907c0ca..2d8e7dba4 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -66,6 +66,13 @@ SimpleTimingPort::recvTiming(Packet *pkt) pkt->makeTimingResponse(); sendTimingLater(pkt, latency); } + else { + if (pkt->cmd != Packet::UpgradeReq) + { + delete pkt->req; + delete pkt; + } + } return true; } |