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authorAlexandru <alexandru.dutu@amd.com>2014-08-28 10:11:44 -0500
committerAlexandru <alexandru.dutu@amd.com>2014-08-28 10:11:44 -0500
commit5efbb4442a0e8c653539e263bf87c48849280e23 (patch)
treeda6807c806ebb1f658692c5bf823156831134c9f /src/mem
parent26ac28dec288e4fd96d999267ec7cafad4d58c5a (diff)
downloadgem5-5efbb4442a0e8c653539e263bf87c48849280e23.tar.xz
mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system memory and respect x86 specification, in SE mode. It defines an architectural page table for x86 as a MultiLevelPageTable class and puts a placeholder class for other ISAs page tables, giving the possibility for future implementation.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/SConscript2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 50b00e8db..dd96879e6 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -65,6 +65,8 @@ if env['TARGET_ISA'] != 'null':
Source('fs_translating_port_proxy.cc')
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
+if env['TARGET_ISA'] == 'x86':
+ Source('multi_level_page_table.cc')
if env['HAVE_DRAMSIM']:
SimObject('DRAMSim2.py')