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authorMarco Elver <marco.elver@ed.ac.uk>2015-06-07 14:02:40 -0500
committerMarco Elver <marco.elver@ed.ac.uk>2015-06-07 14:02:40 -0500
commit6599dd87c8332e4db3d898c9a28531ce2740c37f (patch)
tree6b17c6af452a2473c4f9d96ae2073e00297af65e /src/mem
parent25fe4c25291db84c314ed979b3afbb49a3fa7306 (diff)
downloadgem5-6599dd87c8332e4db3d898c9a28531ce2740c37f.tar.xz
ruby: Fix MESI consistency bug
Fixes missed forward eviction to CPU. With the O3CPU this can lead to load-load reordering, as the LQ is never notified of the invalidate. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/protocol/MESI_Two_Level-L1cache.sm1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index b449c4f2b..4f9928bf1 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -1341,6 +1341,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
// transitions from SM
transition(SM, Inv, IM) {
+ forward_eviction_to_cpu;
fi_sendInvAck;
dg_invalidate_sc;
l_popRequestQueue;