Mem: Change isLlsc to isLLSC.

6 files changed, 15 insertions, 15 deletions

diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index acb117f6c..ab15355bd 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -218,7 +218,7 @@ class CacheBlk
      */
     void trackLoadLocked(PacketPtr pkt)
     {
-        assert(pkt->isLlsc());
+        assert(pkt->isLLSC());
         lockList.push_front(Lock(pkt->req));
     }
 
@@ -236,7 +236,7 @@ class CacheBlk
     bool checkWrite(PacketPtr pkt)
     {
         Request *req = pkt->req;
-        if (pkt->isLlsc()) {
+        if (pkt->isLLSC()) {
             // it's a store conditional... have to check for matching
             // load locked.
             bool success = false;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index f98d6ac34..ea8ae0046 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -180,7 +180,7 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk)
             pkt->writeDataToBlock(blk->data, blkSize);
         }
     } else if (pkt->isRead()) {
-        if (pkt->isLlsc()) {
+        if (pkt->isLLSC()) {
             blk->trackLoadLocked(pkt);
         }
         pkt->setDataFromBlock(blk->data, blkSize);
@@ -317,7 +317,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
 
     incMissCount(pkt);
 
-    if (blk == NULL && pkt->isLlsc() && pkt->isWrite()) {
+    if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) {
         // complete miss on store conditional... just give up now
         pkt->req->setExtraData(0);
         return true;
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 965482c02..b06f53336 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -166,7 +166,7 @@ class MemCmd
     bool isInvalidate() const   { return testCmdAttrib(IsInvalidate); }
     bool hasData() const        { return testCmdAttrib(HasData); }
     bool isReadWrite() const    { return isRead() && isWrite(); }
-    bool isLlsc() const         { return testCmdAttrib(IsLlsc); }
+    bool isLLSC() const         { return testCmdAttrib(IsLlsc); }
     bool isError() const        { return testCmdAttrib(IsError); }
     bool isPrint() const        { return testCmdAttrib(IsPrint); }
 
@@ -401,7 +401,7 @@ class Packet : public FastAlloc, public Printable
     bool isInvalidate() const   { return cmd.isInvalidate(); }
     bool hasData() const        { return cmd.hasData(); }
     bool isReadWrite() const    { return cmd.isReadWrite(); }
-    bool isLlsc() const         { return cmd.isLlsc(); }
+    bool isLLSC() const         { return cmd.isLLSC(); }
     bool isError() const        { return cmd.isError(); }
     bool isPrint() const        { return cmd.isPrint(); }
 
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 86ecb506f..4a521717e 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -162,12 +162,12 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt)
 {
     Request *req = pkt->req;
     Addr paddr = LockedAddr::mask(req->getPaddr());
-    bool isLlsc = pkt->isLlsc();
+    bool isLLSC = pkt->isLLSC();
 
     // Initialize return value.  Non-conditional stores always
     // succeed.  Assume conditional stores will fail until proven
     // otherwise.
-    bool success = !isLlsc;
+    bool success = !isLLSC;
 
     // Iterate over list.  Note that there could be multiple matching
     // records, as more than one context could have done a load locked
@@ -179,7 +179,7 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt)
         if (i->addr == paddr) {
             // we have a matching address
 
-            if (isLlsc && i->matchesContext(req)) {
+            if (isLLSC && i->matchesContext(req)) {
                 // it's a store conditional, and as far as the memory
                 // system can tell, the requesting context's lock is
                 // still valid.
@@ -199,7 +199,7 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt)
         }
     }
 
-    if (isLlsc) {
+    if (isLLSC) {
         req->setExtraData(success ? 1 : 0);
     }
 
@@ -284,7 +284,7 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt)
         TRACE_PACKET("Read/Write");
     } else if (pkt->isRead()) {
         assert(!pkt->isWrite());
-        if (pkt->isLlsc()) {
+        if (pkt->isLLSC()) {
             trackLoadLocked(pkt);
         }
         if (pmemAddr)
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 2a3bea7a5..8dbadccc4 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -129,11 +129,11 @@ class PhysicalMemory : public MemObject
         Request *req = pkt->req;
         if (lockedAddrList.empty()) {
             // no locked addrs: nothing to check, store_conditional fails
-            bool isLlsc = pkt->isLlsc();
-            if (isLlsc) {
+            bool isLLSC = pkt->isLLSC();
+            if (isLLSC) {
                 req->setExtraData(0);
             }
-            return !isLlsc; // only do write if not an sc
+            return !isLLSC; // only do write if not an sc
         } else {
             // iterate over list...
             return checkLockedAddrList(pkt);
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 6e56c07b3..64f6ad053 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -450,7 +450,7 @@ class Request : public FastAlloc
     /** Accessor Function to Check Cacheability. */
     bool isUncacheable() const { return flags.isSet(UNCACHEABLE); }
     bool isInstRead() const { return flags.isSet(INST_READ); }
-    bool isLlsc() const { return flags.isSet(LLSC); }
+    bool isLLSC() const { return flags.isSet(LLSC); }
     bool isLocked() const { return flags.isSet(LOCKED); }
     bool isSwap() const { return flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
     bool isCondSwap() const { return flags.isSet(MEM_SWAP_COND); }