arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

10 files changed, 14 insertions, 4 deletions

diff --git a/src/mem/cache/builder.cc b/src/mem/cache/builder.cc
index 599353b88..bd9eb9acc 100644
--- a/src/mem/cache/builder.cc
+++ b/src/mem/cache/builder.cc
@@ -33,9 +33,10 @@
  * @file
  * Simobject instatiation of caches.
  */
+#include <list>
 #include <vector>
 
-// Must be included first to determine which caches we want
+#include "config/the_isa.hh"
 #include "enums/Prefetch.hh"
 #include "mem/config/cache.hh"
 #include "mem/cache/base.hh"
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index f20a306cb..f0e244a09 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -33,12 +33,14 @@
  * Hardware Prefetcher Definition.
  */
 
+#include <list>
+
 #include "arch/isa_traits.hh"
 #include "base/trace.hh"
+#include "config/the_isa.hh"
 #include "mem/cache/base.hh"
 #include "mem/cache/prefetch/base.hh"
 #include "mem/request.hh"
-#include <list>
 
 BasePrefetcher::BasePrefetcher(const BaseCacheParams *p)
     : size(p->prefetcher_size), pageStop(!p->prefetch_past_page),
diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh
index f70d508b2..fca9606fc 100644
--- a/src/mem/packet_access.hh
+++ b/src/mem/packet_access.hh
@@ -31,6 +31,7 @@
 
 #include "arch/isa_traits.hh"
 #include "base/bigint.hh"
+#include "config/the_isa.hh"
 #include "mem/packet.hh"
 #include "sim/byteswap.hh"
 
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index bf35932a6..4bc3a4434 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -42,6 +42,7 @@
 #include "base/bitfield.hh"
 #include "base/intmath.hh"
 #include "base/trace.hh"
+#include "config/the_isa.hh"
 #include "mem/page_table.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 3ce720ad4..0d93d37c7 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -42,6 +42,7 @@
 #include "arch/tlb.hh"
 #include "base/hashmap.hh"
 #include "base/types.hh"
+#include "config/the_isa.hh"
 #include "mem/request.hh"
 #include "sim/faults.hh"
 #include "sim/serialize.hh"
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index d87ad3b22..be4086cd9 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -44,6 +44,7 @@
 #include "base/random.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "mem/packet_access.hh"
 #include "mem/physical.hh"
 #include "sim/eventq.hh"
diff --git a/src/mem/port_impl.hh b/src/mem/port_impl.hh
index 989cfd338..bc9592164 100644
--- a/src/mem/port_impl.hh
+++ b/src/mem/port_impl.hh
@@ -28,9 +28,8 @@
  * Authors: Ali Saidi
  */
 
-//To get endianness
 #include "arch/isa_traits.hh"
-
+#include "config/the_isa.hh"
 #include "mem/port.hh"
 #include "sim/byteswap.hh"
 
diff --git a/src/mem/rubymem.cc b/src/mem/rubymem.cc
index 4d9f8051f..2fb529e12 100644
--- a/src/mem/rubymem.cc
+++ b/src/mem/rubymem.cc
@@ -35,6 +35,7 @@
 #include "base/output.hh"
 #include "base/str.hh"
 #include "base/types.hh"
+#include "config/the_isa.hh"
 #include "mem/ruby/common/Debug.hh"
 #include "mem/ruby/libruby.hh"
 #include "mem/ruby/system/RubyPort.hh"
diff --git a/src/mem/translating_port.cc b/src/mem/translating_port.cc
index 54de6625e..700229b23 100644
--- a/src/mem/translating_port.cc
+++ b/src/mem/translating_port.cc
@@ -30,7 +30,9 @@
  */
 
 #include <string>
+
 #include "base/chunk_generator.hh"
+#include "config/the_isa.hh"
 #include "mem/port.hh"
 #include "mem/translating_port.hh"
 #include "mem/page_table.hh"
diff --git a/src/mem/vport.cc b/src/mem/vport.cc
index 15be45c2a..ab061c019 100644
--- a/src/mem/vport.cc
+++ b/src/mem/vport.cc
@@ -34,6 +34,7 @@
  */
 
 #include "base/chunk_generator.hh"
+#include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
 #include "mem/vport.hh"