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authorNathan Binkert <nate@binkert.org>2008-10-09 04:58:24 -0700
committerNathan Binkert <nate@binkert.org>2008-10-09 04:58:24 -0700
commite06321091d4e931ff1a4d753e56d76f9746c3cd2 (patch)
tree75e2049ca5ffc65cbfaefa73804571aa933f015b /src/mem
parent8291d9db0a0bdeecb2a13f28962893ed3659230e (diff)
downloadgem5-e06321091d4e931ff1a4d753e56d76f9746c3cd2.tar.xz
eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/bridge.cc12
-rw-r--r--src/mem/bridge.hh5
-rw-r--r--src/mem/bus.cc20
-rw-r--r--src/mem/cache/base.cc2
-rw-r--r--src/mem/cache/cache_impl.hh2
-rw-r--r--src/mem/physical.cc2
-rw-r--r--src/mem/tport.cc2
-rw-r--r--src/mem/tport.hh9
8 files changed, 26 insertions, 28 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 2e668ec32..cc9b83d3e 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -47,7 +47,7 @@ Bridge::BridgePort::BridgePort(const std::string &_name,
int _delay, int _nack_delay, int _req_limit,
int _resp_limit,
std::vector<Range<Addr> > filter_ranges)
- : Port(_name), bridge(_bridge), otherPort(_otherPort),
+ : Port(_name, _bridge), bridge(_bridge), otherPort(_otherPort),
delay(_delay), nackDelay(_nack_delay), filterRanges(filter_ranges),
outstandingResponses(0), queuedRequests(0), inRetry(false),
reqQueueLimit(_req_limit), respQueueLimit(_resp_limit), sendEvent(this)
@@ -162,7 +162,7 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt)
// nothing on the list, add it and we're done
if (sendQueue.empty()) {
assert(!sendEvent.scheduled());
- sendEvent.schedule(readyTime);
+ schedule(sendEvent, readyTime);
sendQueue.push_back(buf);
return;
}
@@ -184,7 +184,7 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt)
while (i != end && !done) {
if (readyTime < (*i)->ready) {
if (i == begin)
- sendEvent.reschedule(readyTime);
+ reschedule(sendEvent, readyTime);
sendQueue.insert(i,buf);
done = true;
}
@@ -227,7 +227,7 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
// should already be an event scheduled for sending the head
// packet.
if (sendQueue.empty()) {
- sendEvent.schedule(readyTime);
+ schedule(sendEvent, readyTime);
}
sendQueue.push_back(buf);
}
@@ -281,7 +281,7 @@ Bridge::BridgePort::trySend()
if (!sendQueue.empty()) {
buf = sendQueue.front();
DPRINTF(BusBridge, "Scheduling next send\n");
- sendEvent.schedule(std::max(buf->ready, curTick + 1));
+ schedule(sendEvent, std::max(buf->ready, curTick + 1));
}
} else {
DPRINTF(BusBridge, " unsuccessful\n");
@@ -302,7 +302,7 @@ Bridge::BridgePort::recvRetry()
if (nextReady <= curTick)
trySend();
else
- sendEvent.schedule(nextReady);
+ schedule(sendEvent, nextReady);
}
/** Function called by the port when the bus is receiving a Atomic
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index a9dd67a2b..40f033811 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -146,11 +146,8 @@ class Bridge : public MemObject
BridgePort *port;
public:
- SendEvent(BridgePort *p)
- : Event(&mainEventQueue), port(p) {}
-
+ SendEvent(BridgePort *p) : port(p) {}
virtual void process() { port->trySend(); }
-
virtual const char *description() const { return "bridge send"; }
};
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 41e9f0ac9..2eb823051 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -97,20 +97,24 @@ Bus::init()
intIter->second->sendStatusChange(Port::RangeChange);
}
-Bus::BusFreeEvent::BusFreeEvent(Bus *_bus) : Event(&mainEventQueue), bus(_bus)
+Bus::BusFreeEvent::BusFreeEvent(Bus *_bus)
+ : bus(_bus)
{}
-void Bus::BusFreeEvent::process()
+void
+Bus::BusFreeEvent::process()
{
bus->recvRetry(-1);
}
-const char * Bus::BusFreeEvent::description() const
+const char *
+Bus::BusFreeEvent::description() const
{
return "bus became available";
}
-Tick Bus::calcPacketTiming(PacketPtr pkt)
+Tick
+Bus::calcPacketTiming(PacketPtr pkt)
{
// Bring tickNextIdle up to the present tick.
// There is some potential ambiguity where a cycle starts, which
@@ -155,12 +159,8 @@ void Bus::occupyBus(Tick until)
}
tickNextIdle = until;
+ reschedule(busIdle, tickNextIdle, true);
- if (!busIdle.scheduled()) {
- busIdle.schedule(tickNextIdle);
- } else {
- busIdle.reschedule(tickNextIdle);
- }
DPRINTF(Bus, "The bus is now occupied from tick %d to %d\n",
curTick, tickNextIdle);
}
@@ -293,7 +293,7 @@ Bus::recvRetry(int id)
//Burn a cycle for the missed grant.
tickNextIdle += clock;
- busIdle.reschedule(tickNextIdle, true);
+ reschedule(busIdle, tickNextIdle, true);
}
}
//If we weren't able to drain before, we might be able to now.
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index ac0d54bf6..956375530 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -122,7 +122,7 @@ BaseCache::CachePort::clearBlocked()
mustSendRetry = false;
SendRetryEvent *ev = new SendRetryEvent(this, true);
// @TODO: need to find a better time (next bus cycle?)
- ev->schedule(curTick + 1);
+ schedule(ev, curTick + 1);
}
}
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 3b56c0a2e..abe3f9b5f 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1489,7 +1489,7 @@ Cache<TagStore>::MemSidePort::sendPacket()
// @TODO: need to facotr in prefetch requests here somehow
if (nextReady != MaxTick) {
DPRINTF(CachePort, "more packets to send @ %d\n", nextReady);
- sendEvent->schedule(std::max(nextReady, curTick + 1));
+ schedule(sendEvent, std::max(nextReady, curTick + 1));
} else {
// no more to send right now: if we're draining, we may be done
if (drainEvent) {
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 325606eb1..20e19669c 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -383,7 +383,7 @@ PhysicalMemory::recvStatusChange(Port::Status status)
PhysicalMemory::MemoryPort::MemoryPort(const std::string &_name,
PhysicalMemory *_memory)
- : SimpleTimingPort(_name), memory(_memory)
+ : SimpleTimingPort(_name, _memory), memory(_memory)
{ }
void
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 15c7fdf9f..254487af8 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -138,7 +138,7 @@ SimpleTimingPort::sendDeferredPacket()
if (success) {
if (!transmitList.empty() && !sendEvent->scheduled()) {
Tick time = transmitList.front().tick;
- sendEvent->schedule(time <= curTick ? curTick+1 : time);
+ schedule(sendEvent, time <= curTick ? curTick+1 : time);
}
if (transmitList.empty() && drainEvent) {
diff --git a/src/mem/tport.hh b/src/mem/tport.hh
index d0f1be425..f1cb5317d 100644
--- a/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@ -108,7 +108,8 @@ class SimpleTimingPort : public Port
Tick deferredPacketReadyTime()
{ return transmitList.empty() ? MaxTick : transmitList.front().tick; }
- void schedSendEvent(Tick when)
+ void
+ schedSendEvent(Tick when)
{
if (waitingOnRetry) {
assert(!sendEvent->scheduled());
@@ -116,9 +117,9 @@ class SimpleTimingPort : public Port
}
if (!sendEvent->scheduled()) {
- sendEvent->schedule(when);
+ schedule(sendEvent, when);
} else if (sendEvent->when() > when) {
- sendEvent->reschedule(when);
+ reschedule(sendEvent, when);
}
}
@@ -155,7 +156,7 @@ class SimpleTimingPort : public Port
public:
- SimpleTimingPort(std::string pname, MemObject *_owner = NULL)
+ SimpleTimingPort(std::string pname, MemObject *_owner)
: Port(pname, _owner),
sendEvent(new SendEvent(this)),
drainEvent(NULL),