sim: Make the drain state a global typed enum

The drain state enum is currently a part of the Drainable
interface. The same state machine will be used by the DrainManager to
identify the global state of the simulator. Make the drain state a
global typed enum to better cater for this usage scenario.

8 files changed, 17 insertions, 17 deletions

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 1d0b9a3dd..e58d5f6b9 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -783,12 +783,12 @@ BaseCache::drain(DrainManager *dm)
 
     // Set status
     if (count != 0) {
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         DPRINTF(Drain, "Cache not drained\n");
         return count;
     }
 
-    setDrainState(Drainable::Drained);
+    setDrainState(DrainState::Drained);
     return 0;
 }
 
diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index f8587e1f1..3736c9f21 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -186,7 +186,7 @@ MSHRQueue::deallocateOne(MSHR *mshr)
         DPRINTF(Drain, "MSHRQueue now empty, signalling drained\n");
         drainManager->signalDrainDone();
         drainManager = NULL;
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     }
     return retval;
 }
@@ -269,11 +269,11 @@ unsigned int
 MSHRQueue::drain(DrainManager *dm)
 {
     if (allocated == 0) {
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
         return 0;
     } else {
         drainManager = dm;
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         return 1;
     }
 }
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 7657cc776..9d264d971 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -2189,9 +2189,9 @@ DRAMCtrl::drain(DrainManager *dm)
     }
 
     if (count)
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     else
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     return count;
 }
 
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index be244bd4a..dfeca0d47 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -362,11 +362,11 @@ DRAMSim2::drain(DrainManager* dm)
     // check our outstanding reads and writes and if any they need to
     // drain
     if (nbrOutstanding() != 0) {
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         drainManager = dm;
         return 1;
     } else {
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
         return 0;
     }
 }
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 43ef37f08..b10538024 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -192,12 +192,12 @@ DMASequencer::drain(DrainManager *dm)
         drainManager = dm;
 
         DPRINTF(Drain, "DMASequencer not drained\n");
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         return child_drain_count + 1;
     }
 
     drainManager = NULL;
-    setDrainState(Drainable::Drained);
+    setDrainState(DrainState::Drained);
     return child_drain_count;
 }
 
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index ec1780c7a..b6aa871b3 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -449,12 +449,12 @@ RubyPort::drain(DrainManager *dm)
         drainManager = dm;
 
         DPRINTF(Drain, "RubyPort not drained\n");
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         return child_drain_count + 1;
     }
 
     drainManager = NULL;
-    setDrainState(Drainable::Drained);
+    setDrainState(DrainState::Drained);
     return child_drain_count;
 }
 
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index b1d22b549..c33f5f819 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -77,7 +77,7 @@ Sequencer::~Sequencer()
 void
 Sequencer::wakeup()
 {
-    assert(getDrainState() != Drainable::Draining);
+    assert(getDrainState() != DrainState::Draining);
 
     // Check for deadlock of any of the requests
     Cycles current_time = curCycle();
@@ -215,7 +215,7 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
 
     // See if we should schedule a deadlock check
     if (!deadlockCheckEvent.scheduled() &&
-        getDrainState() != Drainable::Draining) {
+        getDrainState() != DrainState::Draining) {
         schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
     }
 
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 180339459..f36301809 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -246,9 +246,9 @@ SimpleMemory::drain(DrainManager *dm)
      }
 
     if (count)
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     else
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     return count;
 }