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| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
| commit | fbdeb6031664d71e19a25f51b6ee882d803dac30 (patch) | |
| tree | 0a3fa9a980e9b9a1013b3aff37080b045192b650 /src/mem | |
| parent | bead7f249a71f8b15ae92b0df9822abb52ca7323 (diff) | |
| download | gem5-fbdeb6031664d71e19a25f51b6ee882d803dac30.tar.xz | |
mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.
The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/cache/Cache.py | 2 | ||||
| -rw-r--r-- | src/mem/cache/base.cc | 5 | ||||
| -rw-r--r-- | src/mem/cache/base.hh | 2 |
3 files changed, 5 insertions, 4 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index 531337f19..263b2fea8 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -64,8 +64,6 @@ class BaseCache(MemObject): tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") write_buffers = Param.Unsigned(8, "Number of write buffers") - forward_snoops = Param.Bool(True, - "Forward snoops from mem side to cpu side") is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 41b6f38aa..a3ceaafa3 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -77,7 +77,7 @@ BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) fillLatency(p->response_latency), responseLatency(p->response_latency), numTarget(p->tgts_per_mshr), - forwardSnoops(p->forward_snoops), + forwardSnoops(true), isReadOnly(p->is_read_only), blocked(0), order(0), @@ -86,6 +86,8 @@ BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), system(p->system) { + // forward snoops is overridden in init() once we can query + // whether the connected master is actually snooping or not } void @@ -131,6 +133,7 @@ BaseCache::init() if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) fatal("Cache ports on %s are not connected\n", name()); cpuSidePort->sendRangeChange(); + forwardSnoops = cpuSidePort->isSnooping(); } BaseMasterPort & diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 8cd932f01..1f1f1469f 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -302,7 +302,7 @@ class BaseCache : public MemObject const int numTarget; /** Do we forward snoops from mem side port through to cpu side port? */ - const bool forwardSnoops; + bool forwardSnoops; /** * Is this cache read only, for example the instruction cache, or |