mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.

12 files changed, 79 insertions, 50 deletions

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 16b5148dc..fbab8465e 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1006,7 +1006,8 @@ Cache<TagStore>::writebackBlk(BlkType *blk)
     writebacks[0/*pkt->req->threadId()*/]++;
 
     Request *writebackReq =
-        new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0);
+        new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0,
+                Request::wbMasterId);
     PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, -1);
     if (blk->isWritable()) {
         writeback->setSupplyExclusive();
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index c2c17fa96..fa926e235 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -1,5 +1,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
+from m5.proxy import *
+
 class BasePrefetcher(SimObject):
     type = 'BasePrefetcher'
     abstract = True
@@ -13,10 +15,11 @@ class BasePrefetcher(SimObject):
          "Degree of the prefetch depth")
     latency = Param.Latency('10t',
          "Latency of the prefetcher")
-    use_cpu_id = Param.Bool(True,
-         "Use the CPU ID to separate calculations of prefetches")
+    use_master_id = Param.Bool(True,
+         "Use the master id to separate calculations of prefetches")
     data_accesses_only = Param.Bool(False,
          "Only prefetch on data not on instruction accesses")
+    sys = Param.System(Parent.any, "System this device belongs to")
 
 class GHBPrefetcher(BasePrefetcher):
     type = 'GHBPrefetcher'
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 834787db6..467550823 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -42,11 +42,13 @@
 #include "mem/cache/prefetch/base.hh"
 #include "mem/cache/base.hh"
 #include "mem/request.hh"
+#include "sim/system.hh"
 
 BasePrefetcher::BasePrefetcher(const Params *p)
     : SimObject(p), size(p->size), latency(p->latency), degree(p->degree),
-      useContextId(p->use_cpu_id), pageStop(!p->cross_pages),
-      serialSquash(p->serial_squash), onlyData(p->data_accesses_only)
+      useMasterId(p->use_master_id), pageStop(!p->cross_pages),
+      serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
+      system(p->sys), masterId(system->getMasterId(name()))
 {
 }
 
@@ -230,7 +232,7 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick time)
             }
 
             // create a prefetch memreq
-            Request *prefetchReq = new Request(*addrIter, blkSize, 0);
+            Request *prefetchReq = new Request(*addrIter, blkSize, 0, masterId);
             PacketPtr prefetch =
                 new Packet(prefetchReq, MemCmd::HardPFReq, Packet::Broadcast);
             prefetch->allocate();
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index ead163215..1517be50c 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -70,7 +70,7 @@ class BasePrefetcher : public SimObject
     unsigned degree;
 
     /** If patterns should be found per context id */
-    bool useContextId;
+    bool useMasterId;
     /** Do we prefetch across page boundaries. */
     bool pageStop;
 
@@ -80,6 +80,12 @@ class BasePrefetcher : public SimObject
     /** Do we prefetch on only data reads, or on inst reads as well. */
     bool onlyData;
 
+    /** System we belong to */
+    System* system;
+
+    /** Request id for prefetches */
+    MasterID masterId;
+
   public:
 
     Stats::Scalar pfIdentified;
diff --git a/src/mem/cache/prefetch/ghb.cc b/src/mem/cache/prefetch/ghb.cc
index b9fc8e675..8e42a4e2b 100644
--- a/src/mem/cache/prefetch/ghb.cc
+++ b/src/mem/cache/prefetch/ghb.cc
@@ -42,20 +42,15 @@ void
 GHBPrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
                                  std::list<Tick> &delays)
 {
-    if (useContextId && !pkt->req->hasContextId()) {
-        DPRINTF(HWPrefetch, "ignoring request with no context ID");
-        return;
-    }
-
     Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
-    int ctx_id = useContextId ? pkt->req->contextId() : 0;
-    assert(ctx_id < Max_Contexts);
+    int master_id = useMasterId ? pkt->req->masterId() : 0;
+    assert(master_id < Max_Masters);
 
-    int new_stride = blk_addr - lastMissAddr[ctx_id];
-    int old_stride = lastMissAddr[ctx_id] - secondLastMissAddr[ctx_id];
+    int new_stride = blk_addr - lastMissAddr[master_id];
+    int old_stride = lastMissAddr[master_id] - secondLastMissAddr[master_id];
 
-    secondLastMissAddr[ctx_id] = lastMissAddr[ctx_id];
-    lastMissAddr[ctx_id] = blk_addr;
+    secondLastMissAddr[master_id] = lastMissAddr[master_id];
+    lastMissAddr[master_id] = blk_addr;
 
     if (new_stride == old_stride) {
         for (int d = 1; d <= degree; d++) {
diff --git a/src/mem/cache/prefetch/ghb.hh b/src/mem/cache/prefetch/ghb.hh
index a21b57b93..ff713876a 100644
--- a/src/mem/cache/prefetch/ghb.hh
+++ b/src/mem/cache/prefetch/ghb.hh
@@ -43,10 +43,10 @@ class GHBPrefetcher : public BasePrefetcher
 {
   protected:
 
-    static const int Max_Contexts = 64;
+    static const int Max_Masters = 64;
 
-    Addr secondLastMissAddr[Max_Contexts];
-    Addr lastMissAddr[Max_Contexts];
+    Addr secondLastMissAddr[Max_Masters];
+    Addr lastMissAddr[Max_Masters];
 
   public:
     GHBPrefetcher(const Params *p)
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index 645bc5fc5..feaa9494e 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -47,16 +47,11 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
         return;
     }
 
-    if (useContextId && !pkt->req->hasContextId()) {
-        DPRINTF(HWPrefetch, "ignoring request with no context ID");
-        return;
-    }
-
     Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
-    int ctx_id = useContextId ? pkt->req->contextId() : 0;
+    MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
     Addr pc = pkt->req->getPC();
-    assert(ctx_id < Max_Contexts);
-    std::list<StrideEntry*> &tab = table[ctx_id];
+    assert(master_id < Max_Contexts);
+    std::list<StrideEntry*> &tab = table[master_id];
 
     /* Scan Table for instAddr Match */
     std::list<StrideEntry*>::iterator iter;
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index acce3ffc8..3501ec378 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -369,7 +369,7 @@ IIC::freeReplacementBlock(PacketList & writebacks)
                                   tag_ptr->size);
 */
             Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
-                                           blkSize, 0);
+                                           blkSize, 0, Request::wbMasterId);
             PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback,
                                              -1);
             writeback->allocate();
diff --git a/src/mem/port.cc b/src/mem/port.cc
index fb1715db6..e489b9d7a 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -70,7 +70,7 @@ Port::blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd)
 
     for (ChunkGenerator gen(addr, size, peerBlockSize());
          !gen.done(); gen.next()) {
-        req.setPhys(gen.addr(), gen.size(), 0);
+        req.setPhys(gen.addr(), gen.size(), 0, Request::funcMasterId);
         Packet pkt(&req, cmd, Packet::Broadcast);
         pkt.dataStatic(p);
         sendFunctional(&pkt);
@@ -106,7 +106,7 @@ Port::memsetBlob(Addr addr, uint8_t val, int size)
 void
 Port::printAddr(Addr a)
 {
-    Request req(a, 1, 0);
+    Request req(a, 1, 0, Request::funcMasterId);
     Packet pkt(&req, MemCmd::PrintReq, Packet::Broadcast);
     Packet::PrintReqState prs(std::cerr);
     pkt.senderState = &prs;
diff --git a/src/mem/request.hh b/src/mem/request.hh
index dce68087d..b6128f450 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -50,6 +50,7 @@
 class Request;
 
 typedef Request* RequestPtr;
+typedef uint16_t MasterID;
 
 class Request : public FastAlloc
 {
@@ -100,6 +101,18 @@ class Request : public FastAlloc
        (assigned a new address). */
     static const FlagsType STICKY_FLAGS = INST_FETCH;
 
+    /** Request Ids that are statically allocated
+     * @{*/
+    /** This request id is used for writeback requests by the caches */
+    static const MasterID wbMasterId = 0;
+    /** This request id is used for functional requests that don't come from a
+     * particular device
+     */
+    static const MasterID funcMasterId = 1;
+    /** This request id is used for message signaled interrupts */
+    static const MasterID intMasterId = 2;
+    /** @} */
+
   private:
     typedef uint8_t PrivateFlagsType;
     typedef ::Flags<PrivateFlagsType> PrivateFlags;
@@ -137,6 +150,11 @@ class Request : public FastAlloc
      */
     int _size;
 
+    /** The requestor ID which is unique in the system for all ports
+     * that are capable of issuing a transaction
+     */
+    MasterID _masterId;
+
     /** Flag structure for the request. */
     Flags _flags;
 
@@ -182,27 +200,27 @@ class Request : public FastAlloc
      * just physical address, size, flags, and timestamp (to curTick()).
      * These fields are adequate to perform a request. 
      */
-    Request(Addr paddr, int size, Flags flags)
+    Request(Addr paddr, int size, Flags flags, MasterID mid)
     {
-        setPhys(paddr, size, flags);
+        setPhys(paddr, size, flags, mid);
     }
 
-    Request(Addr paddr, int size, Flags flags, Tick time)
+    Request(Addr paddr, int size, Flags flags, MasterID mid, Tick time)
     {
-        setPhys(paddr, size, flags, time);
+        setPhys(paddr, size, flags, mid, time);
     }
 
-    Request(Addr paddr, int size, Flags flags, Tick time, Addr pc)
+    Request(Addr paddr, int size, Flags flags, MasterID mid, Tick time, Addr pc)
     {
-        setPhys(paddr, size, flags, time);
+        setPhys(paddr, size, flags, mid, time);
         privateFlags.set(VALID_PC);
         _pc = pc;
     }
 
-    Request(int asid, Addr vaddr, int size, Flags flags, Addr pc,
+    Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
             int cid, ThreadID tid)
     {
-        setVirt(asid, vaddr, size, flags, pc);
+        setVirt(asid, vaddr, size, flags, mid, pc);
         setThreadContext(cid, tid);
     }
 
@@ -224,13 +242,13 @@ class Request : public FastAlloc
      * allocated Request object.
      */
     void
-    setPhys(Addr paddr, int size, Flags flags, Tick time)
+    setPhys(Addr paddr, int size, Flags flags, MasterID mid, Tick time)
     {
         assert(size >= 0);
         _paddr = paddr;
         _size = size;
         _time = time;
-
+        _masterId = mid;
         _flags.clear(~STICKY_FLAGS);
         _flags.set(flags);
         privateFlags.clear(~STICKY_PRIVATE_FLAGS);
@@ -238,9 +256,9 @@ class Request : public FastAlloc
     }
 
     void
-    setPhys(Addr paddr, int size, Flags flags)
+    setPhys(Addr paddr, int size, Flags flags, MasterID mid)
     {
-        setPhys(paddr, size, flags, curTick());
+        setPhys(paddr, size, flags, mid, curTick());
     }
 
     /**
@@ -248,12 +266,13 @@ class Request : public FastAlloc
      * allocated Request object.
      */
     void
-    setVirt(int asid, Addr vaddr, int size, Flags flags, Addr pc)
+    setVirt(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc)
     {
         assert(size >= 0);
         _asid = asid;
         _vaddr = vaddr;
         _size = size;
+        _masterId = mid;
         _pc = pc;
         _time = curTick();
 
@@ -369,6 +388,13 @@ class Request : public FastAlloc
         return _vaddr;
     }
 
+    /** Accesssor for the requestor id. */
+    MasterID
+    masterId()
+    {
+        return _masterId;
+    }
+
     /** Accessor function for asid.*/
     int
     getAsid()
diff --git a/src/mem/ruby/recorder/CacheRecorder.cc b/src/mem/ruby/recorder/CacheRecorder.cc
index 8b724859e..a886f3238 100644
--- a/src/mem/ruby/recorder/CacheRecorder.cc
+++ b/src/mem/ruby/recorder/CacheRecorder.cc
@@ -74,7 +74,8 @@ CacheRecorder::enqueueNextFlushRequest()
         TraceRecord* rec = m_records[m_records_flushed];
         m_records_flushed++;
         Request* req = new Request(rec->m_data_address,
-                                   RubySystem::getBlockSizeBytes(),0);
+                                   RubySystem::getBlockSizeBytes(),0,
+                                   Request::funcMasterId);
         MemCmd::Command requestType = MemCmd::FlushReq;
         Packet *pkt = new Packet(req, requestType, -1);
 
@@ -100,16 +101,16 @@ CacheRecorder::enqueueNextFetchRequest()
         if (traceRecord->m_type == RubyRequestType_LD) {
             requestType = MemCmd::ReadReq;
             req->setPhys(traceRecord->m_data_address,
-                    RubySystem::getBlockSizeBytes(),0);
+                    RubySystem::getBlockSizeBytes(),0, Request::funcMasterId);
         }   else if (traceRecord->m_type == RubyRequestType_IFETCH) {
             requestType = MemCmd::ReadReq;
             req->setPhys(traceRecord->m_data_address,
                     RubySystem::getBlockSizeBytes(),
-                    Request::INST_FETCH);
+                    Request::INST_FETCH, Request::funcMasterId);
         }   else {
             requestType = MemCmd::WriteReq;
             req->setPhys(traceRecord->m_data_address,
-                    RubySystem::getBlockSizeBytes(),0);
+                    RubySystem::getBlockSizeBytes(),0, Request::funcMasterId);
         }
 
         Packet *pkt = new Packet(req, requestType, -1);
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index af414f17a..ab3e6e3b7 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -687,7 +687,7 @@ void
 RubyPort::ruby_eviction_callback(const Address& address)
 {
     DPRINTF(RubyPort, "Sending invalidations.\n");
-    Request req(address.getAddress(), 0, 0);
+    Request req(address.getAddress(), 0, 0, Request::funcMasterId);
     for (CpuPortIter it = cpu_ports.begin(); it != cpu_ports.end(); it++) {
         Packet *pkt = new Packet(&req, MemCmd::InvalidationReq, -1);
         (*it)->sendTiming(pkt);