diff options
| author | yuetsu.kodama <yuetsu.kodama@riken.jp> | 2018-10-20 11:58:54 +0900 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-10-26 12:47:46 +0000 |
| commit | 59e3585a84ef172eba57c9936680c0248f9a97db (patch) | |
| tree | 8bf691977e16156e5d05d18c087cb2a77af19212 /src/mem | |
| parent | d4b3e064adeeace3c3e7d106801f95c14637c12f (diff) | |
| download | gem5-59e3585a84ef172eba57c9936680c0248f9a97db.tar.xz | |
arch-arm: We add PRFM PST instruction for arm
Note current PRFM supports only PLD, but PST (prefetch for store) is
also important for latency hiding. We also bug fix in disassembler to
display prfop correctly.
Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13
Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp>
Reviewed-on: https://gem5-review.googlesource.com/c/13675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/cache/base.cc | 2 | ||||
| -rw-r--r-- | src/mem/packet.cc | 3 | ||||
| -rw-r--r-- | src/mem/packet.hh | 3 | ||||
| -rw-r--r-- | src/mem/request.hh | 4 |
4 files changed, 10 insertions, 2 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index ed23ffde2..7bb0e0fdb 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -1663,7 +1663,7 @@ BaseCache::regStats() // should writebacks be included here? prior code was inconsistent... #define SUM_NON_DEMAND(s) \ - (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) + (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq] + s[MemCmd::SoftPFExReq]) demandHits .name(name() + ".demand_hits") diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 866bc9051..4369e168f 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -105,6 +105,9 @@ MemCmd::commandInfo[] = /* SoftPFReq */ { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse), SoftPFResp, "SoftPFReq" }, + /* SoftPFExReq */ + { SET6(IsRead, NeedsWritable, IsInvalidate, IsRequest, + IsSWPrefetch, NeedsResponse), SoftPFResp, "SoftPFExReq" }, /* HardPFReq */ { SET5(IsRead, IsRequest, IsHWPrefetch, NeedsResponse, FromCache), HardPFResp, "HardPFReq" }, diff --git a/src/mem/packet.hh b/src/mem/packet.hh index f0b7c2f2f..c59db362e 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -94,6 +94,7 @@ class MemCmd WriteClean, // writes dirty data below without evicting CleanEvict, SoftPFReq, + SoftPFExReq, HardPFReq, SoftPFResp, HardPFResp, @@ -859,6 +860,8 @@ class Packet : public Printable { if (req->isLLSC()) return MemCmd::LoadLockedReq; + else if (req->isPrefetchEx()) + return MemCmd::SoftPFExReq; else if (req->isPrefetch()) return MemCmd::SoftPFReq; else diff --git a/src/mem/request.hh b/src/mem/request.hh index 3df29aa1c..2a53c21a4 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -860,7 +860,9 @@ class Request bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); } bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); } bool isInstFetch() const { return _flags.isSet(INST_FETCH); } - bool isPrefetch() const { return _flags.isSet(PREFETCH); } + bool isPrefetch() const { return (_flags.isSet(PREFETCH) || + _flags.isSet(PF_EXCLUSIVE)); } + bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); } bool isLLSC() const { return _flags.isSet(LLSC); } bool isPriv() const { return _flags.isSet(PRIVILEGED); } bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); } |