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authorAndreas Hansson <andreas.hansson@arm.com>2015-08-21 07:03:23 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-08-21 07:03:23 -0400
commitddfa96cf455ba4a287930942514cdf0f7f2afa77 (patch)
tree89eddf6ab0ec6f4660629b45b1b7cff7df6ca82c /src/mem
parentd71a0d790d8d1113480c5a57d7bfbb9b7d0d0037 (diff)
downloadgem5-ddfa96cf455ba4a287930942514cdf0f7f2afa77.tar.xz
mem: Add explicit Cache subclass and make BaseCache abstract
Open up for other subclasses to BaseCache and transition to using the explicit Cache subclass. --HG-- rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/Cache.py (renamed from src/mem/cache/BaseCache.py)6
-rw-r--r--src/mem/cache/SConscript2
-rw-r--r--src/mem/cache/base.cc12
-rw-r--r--src/mem/cache/base.hh3
-rw-r--r--src/mem/cache/cache.cc11
-rw-r--r--src/mem/cache/cache.hh3
6 files changed, 21 insertions, 16 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/Cache.py
index d908430e5..8ad1177e7 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/Cache.py
@@ -37,6 +37,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
+# Andreas Hansson
from m5.params import *
from m5.proxy import *
@@ -46,6 +47,7 @@ from Tags import *
class BaseCache(MemObject):
type = 'BaseCache'
+ abstract = True
cxx_header = "mem/cache/base.hh"
size = Param.MemorySize("Capacity")
@@ -81,3 +83,7 @@ class BaseCache(MemObject):
"Address range for the CPU-side port (to allow striping)")
system = Param.System(Parent.any, "System we belong to")
+
+class Cache(BaseCache):
+ type = 'Cache'
+ cxx_header = 'mem/cache/cache.hh'
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index a4fbe04c0..1c356ef6a 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -30,7 +30,7 @@
Import('*')
-SimObject('BaseCache.py')
+SimObject('Cache.py')
Source('base.cc')
Source('cache.cc')
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index c270d5b65..41b6f38aa 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -65,13 +65,13 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
{
}
-BaseCache::BaseCache(const Params *p)
+BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
: MemObject(p),
cpuSidePort(nullptr), memSidePort(nullptr),
mshrQueue("MSHRs", p->mshrs, 4, p->demand_mshr_reserve, MSHRQueue_MSHRs),
writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0,
MSHRQueue_WriteBuffer),
- blkSize(p->system->cacheLineSize()),
+ blkSize(blk_size),
lookupLatency(p->hit_latency),
forwardLatency(p->hit_latency),
fillLatency(p->response_latency),
@@ -774,11 +774,3 @@ BaseCache::regStats()
;
}
-
-BaseCache *
-BaseCacheParams::create()
-{
- assert(tags);
-
- return new Cache(this);
-}
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 3e6f5cab2..3baec36d9 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -473,8 +473,7 @@ class BaseCache : public MemObject
virtual void regStats();
public:
- typedef BaseCacheParams Params;
- BaseCache(const Params *p);
+ BaseCache(const BaseCacheParams *p, unsigned blk_size);
~BaseCache() {}
virtual void init();
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 2426a0636..911785479 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -63,8 +63,8 @@
#include "mem/cache/prefetch/base.hh"
#include "sim/sim_exit.hh"
-Cache::Cache(const Params *p)
- : BaseCache(p),
+Cache::Cache(const CacheParams *p)
+ : BaseCache(p, p->system->cacheLineSize()),
tags(p->tags),
prefetcher(p->prefetcher),
doFastWrites(true),
@@ -2382,6 +2382,13 @@ CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache,
{
}
+Cache*
+CacheParams::create()
+{
+ assert(tags);
+
+ return new Cache(this);
+}
///////////////
//
// MemSidePort
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 06d78a272..447a55229 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -57,6 +57,7 @@
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/tags/base.hh"
+#include "params/Cache.hh"
#include "sim/eventq.hh"
//Forward decleration
@@ -419,7 +420,7 @@ class Cache : public BaseCache
public:
/** Instantiates a basic cache object. */
- Cache(const Params *p);
+ Cache(const CacheParams *p);
/** Non-default destructor is needed to deallocate memory. */
virtual ~Cache();