Merge with head, hopefully the last time for this batch.

11 files changed, 17 insertions, 31 deletions

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index a20f90108..dfe4be3cc 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -436,7 +436,8 @@ Bus::recvFunctional(PacketPtr pkt)
         pkt->setSrc(src_id);
     }
 
-    // If the snooping hasn't found what we were looking for, keep going.
+    // If the snooping hasn't found what we were looking for and it is not
+    // a forwarded snoop from below, keep going.
     if (!pkt->isResponse() && port_id != pkt->getSrc()) {
         port->sendFunctional(pkt);
     }
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 2b7fa4b9f..b0fb3bc6c 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -45,8 +45,7 @@ using namespace std;
 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
                                 const std::string &_label)
     : SimpleTimingPort(_name, _cache), cache(_cache),
-      label(_label), otherPort(NULL),
-      blocked(false), mustSendRetry(false)
+      label(_label), blocked(false), mustSendRetry(false)
 {
 }
 
@@ -70,12 +69,6 @@ BaseCache::BaseCache(const Params *p)
 {
 }
 
-void
-BaseCache::CachePort::recvRangeChange() const
-{
-    otherPort->sendRangeChange();
-}
-
 
 bool
 BaseCache::CachePort::checkFunctional(PacketPtr pkt)
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index fded6fca6..3aaed4455 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -73,6 +73,7 @@ class BaseCache : public MemObject
         MSHRQueue_WriteBuffer
     };
 
+  public:
     /**
      * Reasons for caches to be blocked.
      */
@@ -83,7 +84,6 @@ class BaseCache : public MemObject
         NUM_BLOCKED_CAUSES
     };
 
-  public:
     /**
      * Reasons for cache to request a bus.
      */
@@ -94,7 +94,7 @@ class BaseCache : public MemObject
         NUM_REQUEST_CAUSES
     };
 
-  private:
+  protected:
 
     class CachePort : public SimpleTimingPort
     {
@@ -105,8 +105,6 @@ class BaseCache : public MemObject
         CachePort(const std::string &_name, BaseCache *_cache,
                   const std::string &_label);
 
-        virtual void recvRangeChange() const;
-
         virtual unsigned deviceBlockSize() const;
 
         bool recvRetryCommon();
@@ -117,16 +115,12 @@ class BaseCache : public MemObject
         const std::string label;
 
       public:
-        void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; }
-
         void setBlocked();
 
         void clearBlocked();
 
         bool checkFunctional(PacketPtr pkt);
 
-        CachePort *otherPort;
-
         bool blocked;
 
         bool mustSendRetry;
@@ -144,7 +138,6 @@ class BaseCache : public MemObject
         }
     };
 
-  public: //Made public so coherence can get at it.
     CachePort *cpuSidePort;
     CachePort *memSidePort;
 
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 13484eb79..2ef53e040 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -77,8 +77,6 @@ Cache<TagStore>::Cache(const Params *p, TagStore *tags, BasePrefetcher *pf)
                                   "CpuSidePort");
     memSidePort = new MemSidePort(p->name + "-mem_side_port", this,
                                   "MemSidePort");
-    cpuSidePort->setOtherPort(memSidePort);
-    memSidePort->setOtherPort(cpuSidePort);
 
     tags->setCache(this);
     if (prefetcher)
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 71c3ba48c..acce3ffc8 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -187,7 +187,7 @@ IIC::regStats(const string &name)
         .flags(pdf)
         ;
 
-    repl->regStats(name);
+    repl->regStatsWithSuffix(name);
 
     if (PROFILE_IIC)
         setAccess
diff --git a/src/mem/cache/tags/iic_repl/gen.cc b/src/mem/cache/tags/iic_repl/gen.cc
index 7a1e7a110..137130b27 100644
--- a/src/mem/cache/tags/iic_repl/gen.cc
+++ b/src/mem/cache/tags/iic_repl/gen.cc
@@ -184,7 +184,7 @@ GenRepl::add(unsigned long tag_index)
 }
 
 void
-GenRepl::regStats(const string name)
+GenRepl::regStatsWithSuffix(const string name)
 {
     using namespace Stats;
 
diff --git a/src/mem/cache/tags/iic_repl/gen.hh b/src/mem/cache/tags/iic_repl/gen.hh
index fe105d95a..cbd15a6fd 100644
--- a/src/mem/cache/tags/iic_repl/gen.hh
+++ b/src/mem/cache/tags/iic_repl/gen.hh
@@ -209,7 +209,7 @@ class GenRepl : public Repl
      * Register statistics.
      * @param name The name to prepend to statistic descriptions.
      */
-    virtual void regStats(const std::string name);
+    virtual void regStatsWithSuffix(const std::string name);
 
     /**
      * Update the tag pointer to when the tag moves.
diff --git a/src/mem/cache/tags/iic_repl/repl.hh b/src/mem/cache/tags/iic_repl/repl.hh
index 994af5164..51d8169e9 100644
--- a/src/mem/cache/tags/iic_repl/repl.hh
+++ b/src/mem/cache/tags/iic_repl/repl.hh
@@ -102,7 +102,7 @@ class Repl : public SimObject
      * Register statistics.
      * @param name The name to prepend to statistic descriptions.
      */
-    virtual void regStats(const std::string name) = 0;
+    virtual void regStatsWithSuffix(const std::string name) = 0;
 
     /**
      * Update the tag pointer to when the tag moves.
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index e49ce7577..ce5748c24 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -53,7 +53,7 @@
 #include "mem/request.hh"
 #include "sim/core.hh"
 
-struct Packet;
+class Packet;
 typedef Packet *PacketPtr;
 typedef uint8_t* PacketDataPtr;
 typedef std::list<PacketPtr> PacketList;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
index aee05b696..126c5c811 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
@@ -104,11 +104,12 @@ GarnetNetwork_d::init()
         for (vector<Router_d*>::const_iterator i= m_router_ptr_vector.begin();
              i != m_router_ptr_vector.end(); ++i) {
             Router_d* router = safe_cast<Router_d*>(*i);
-            int router_id=fault_model->declare_router(router->get_num_inports(),
-                                                      router->get_num_outports(),
-                                                      router->get_vc_per_vnet(),
-                                                      getBuffersPerDataVC(),
-                                                      getBuffersPerCtrlVC());
+            int router_id M5_VAR_USED =
+                fault_model->declare_router(router->get_num_inports(),
+                                            router->get_num_outports(),
+                                            router->get_vc_per_vnet(),
+                                            getBuffersPerDataVC(),
+                                            getBuffersPerCtrlVC());
             assert(router_id == router->get_id());
             router->printAggregateFaultProbability(cout);
             router->printFaultVector(cout);
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index e262e32e8..296258994 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -41,7 +41,7 @@
 class DataBlock;
 class CacheMemory;
 
-class RubySequencerParams;
+struct RubySequencerParams;
 
 struct SequencerRequest
 {