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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-10-02 14:35:44 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-10-02 14:35:44 -0500 |
commit | b370f6a7b2fb9a4cd8e38b1db12845d401d3adf3 (patch) | |
tree | c51131cdc9e0af5544527446b602c726f2a02acb /src/mem | |
parent | d58f84c481093aa34d08079f9f8dd6700114e767 (diff) | |
download | gem5-b370f6a7b2fb9a4cd8e38b1db12845d401d3adf3.tar.xz |
ruby: rename template_hack to template
I don't like using the word hack. Hence, the patch.
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L1cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L2cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-dir.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MI_example-dir.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 4 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dir.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dma.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_token-L1cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_token-L2cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_token-dir.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_hammer-dir.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/Network_test-cache.sm | 2 | ||||
-rw-r--r-- | src/mem/slicc/symbols/StateMachine.py | 4 |
16 files changed, 18 insertions, 18 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index 1316a0ed4..d54f7e71c 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -126,7 +126,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") bool isPresent(Address); } - TBETable L1_TBEs, template_hack="<L1Cache_TBE>"; + TBETable L1_TBEs, template="<L1Cache_TBE>"; MessageBuffer mandatoryQueue, ordered="false"; diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm index 256f671f9..88053aeb8 100644 --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm @@ -151,7 +151,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") bool isPresent(Address); } - TBETable L2_TBEs, template_hack="<L2Cache_TBE>"; + TBETable L2_TBEs, template="<L2Cache_TBE>"; void set_cache_entry(AbstractCacheEntry a); void unset_cache_entry(); diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm index aa1294b2c..7e1280337 100644 --- a/src/mem/protocol/MESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MESI_CMP_directory-dir.sm @@ -105,7 +105,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") // ** OBJECTS ** - TBETable TBEs, template_hack="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>"; void set_tbe(TBE tbe); void unset_tbe(); diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 89f8cbed1..cf5cf9505 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -98,7 +98,7 @@ machine(L1Cache, "MI Example L1 Cache") // STRUCTURES - TBETable TBEs, template_hack="<L1Cache_TBE>"; + TBETable TBEs, template="<L1Cache_TBE>"; // PROTOTYPES void set_cache_entry(AbstractCacheEntry a); diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm index 617d13ba9..241ad3b30 100644 --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -102,7 +102,7 @@ machine(Directory, "Directory protocol") } // ** OBJECTS ** - TBETable TBEs, template_hack="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>"; void set_tbe(TBE b); void unset_tbe(); diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 7a5cc6511..43c2def2e 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -142,7 +142,7 @@ machine(L1Cache, "Directory protocol") MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true"; - TBETable TBEs, template_hack="<L1Cache_TBE>"; + TBETable TBEs, template="<L1Cache_TBE>"; TimerTable useTimerTable; int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index eb9693ed9..6238953ad 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -225,8 +225,8 @@ machine(L2Cache, "Token protocol") } - TBETable TBEs, template_hack="<L2Cache_TBE>"; - PerfectCacheMemory localDirectory, template_hack="<L2Cache_DirEntry>"; + TBETable TBEs, template="<L2Cache_TBE>"; + PerfectCacheMemory localDirectory, template="<L2Cache_DirEntry>"; void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index 02e3d3635..1635267f6 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -119,7 +119,7 @@ machine(Directory, "Directory protocol") } // ** OBJECTS ** - TBETable TBEs, template_hack="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>"; void set_tbe(TBE b); void unset_tbe(); diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index 36b89056c..e0a8a3eb5 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -44,7 +44,7 @@ machine(DMA, "DMA Controller") MessageBuffer mandatoryQueue, ordered="false"; MessageBuffer triggerQueue, ordered="true"; - TBETable TBEs, template_hack="<DMA_TBE>"; + TBETable TBEs, template="<DMA_TBE>"; State cur_state; void set_tbe(TBE b); diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index 7cc41cc20..b6de5a714 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -180,7 +180,7 @@ machine(L1Cache, "Token protocol") void wakeUpAllBuffers(); void wakeUpBuffers(Address a); - TBETable L1_TBEs, template_hack="<L1Cache_TBE>"; + TBETable L1_TBEs, template="<L1Cache_TBE>"; MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true"; diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm index 078b5c7a6..411390a5e 100644 --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm @@ -146,7 +146,7 @@ machine(L2Cache, "Token protocol") } PersistentTable persistentTable; - PerfectCacheMemory localDirectory, template_hack="<L2Cache_DirEntry>"; + PerfectCacheMemory localDirectory, template="<L2Cache_DirEntry>"; void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm index 39e8a8d27..8d78be40c 100644 --- a/src/mem/protocol/MOESI_CMP_token-dir.sm +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm @@ -157,7 +157,7 @@ machine(Directory, "Token protocol") PersistentTable persistentTable; TimerTable reissueTimerTable; - TBETable TBEs, template_hack="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>"; bool starving, default="false"; int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 1fe353ce5..6eb0974b0 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -173,7 +173,7 @@ machine(L1Cache, "AMD Hammer-like protocol") bool isPresent(Address); } - TBETable TBEs, template_hack="<L1Cache_TBE>"; + TBETable TBEs, template="<L1Cache_TBE>"; void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm index 1fc946386..ed1fb7669 100644 --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -184,7 +184,7 @@ machine(Directory, "AMD Hammer-like protocol") Set fwd_set; - TBETable TBEs, template_hack="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>"; Entry getDirectoryEntry(Address addr), return_by_pointer="yes" { Entry dir_entry := static_cast(Entry, "pointer", directory[addr]); diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm index d3b649e89..64b156938 100644 --- a/src/mem/protocol/Network_test-cache.sm +++ b/src/mem/protocol/Network_test-cache.sm @@ -82,7 +82,7 @@ machine(L1Cache, "Network_test L1 Cache") // STRUCTURES - TBETable TBEs, template_hack="<L1Cache_TBE>"; + TBETable TBEs, template="<L1Cache_TBE>"; // FUNCTIONS diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 2b1e2a2b5..bb69b70bf 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -385,7 +385,7 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr); // Objects ''') for var in self.objects: - th = var.get("template_hack", "") + th = var.get("template", "") code('${{var.type.c_ident}}$th* m_${{var.c_ident}}_ptr;') if var.type.ident == "MessageBuffer": @@ -568,7 +568,7 @@ $c_ident::init() if "factory" in var: code('$vid = ${{var["factory"]}};') elif var.ident.find("mandatoryQueue") < 0: - th = var.get("template_hack", "") + th = var.get("template", "") expr = "%s = new %s%s" % (vid, vtype.c_ident, th) args = "" |