diff options
| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-07 12:55:37 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-07 12:55:37 -0400 |
| commit | 467c17fbd9b6ff4780e11182de26aaaa74ac06d8 (patch) | |
| tree | ecb2d74fd0c72b684dd37beadc341ce563440470 /src/mem | |
| parent | fdaed2c7aeb0f2a34c6ef60cc7de7db8d8db62b3 (diff) | |
| download | gem5-467c17fbd9b6ff4780e11182de26aaaa74ac06d8.tar.xz | |
Fix a missing pointer
--HG--
extra : convert_revision : 2056b530d48fd004ab700f09e58f44adae3ea0e9
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/cache/base_cache.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 4b62073d8..d7ccca8c0 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -211,7 +211,7 @@ BaseCache::CacheEvent::process() //Know the packet to send pkt->result = Packet::Success; pkt->makeTimingResponse(); - if (!drainList.empty()) { + if (!cachePort->drainList.empty()) { //Already blocked waiting for bus, just append cachePort->drainList.push_back(pkt); } |