ruby: cleaned up unified MESI/MOESI configuration

3 files changed, 60 insertions, 70 deletions

diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
index e20b7249e..b44813ab6 100644
--- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
+++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
@@ -26,6 +26,7 @@ num_memories = 1
 memory_size_mb = 1024
 num_dma = 1
 
+#default protocol 
 protocol = "MESI_CMP_directory"
 
 # check for overrides
@@ -56,7 +57,7 @@ end
 net_ports = Array.new
 iface_ports = Array.new
 
-#assert(protocol == "MESI_CMP_directory", __FILE__+" cannot be used with protocol "+protocol);
+assert((protocol == "MESI_CMP_directory" or protocol == "MOESI_CMP_directory"), __FILE__+" cannot be used with protocol "+protocol);
 
 require protocol+".rb"
 
@@ -71,9 +72,7 @@ num_cores.times { |n|
                                                            icache, dcache,
                                                            sequencer,
                                                            num_l2_banks)
-  end
-
-  if protocol == "MESI_CMP_directory"
+  elsif protocol == "MESI_CMP_directory"
     net_ports << MESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s,
                                                            "L1Cache",
                                                            icache, dcache,
@@ -87,17 +86,14 @@ num_l2_banks.times { |n|
     net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
                                                            "L2Cache",
                                                            cache)
-    net_ports.last.request_latency = l2_cache_latency + 2
-    net_ports.last.response_latency = l2_cache_latency + 2
-  end
-
-  if protocol == "MESI_CMP_directory"
+  elsif protocol == "MESI_CMP_directory"
     net_ports << MESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
                                                            "L2Cache",
                                                            cache)
   end
 
-
+  net_ports.last.request_latency = l2_cache_latency + 2
+  net_ports.last.response_latency = l2_cache_latency + 2
 }
 num_memories.times { |n|
   directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories)
@@ -107,9 +103,7 @@ num_memories.times { |n|
                                                              "Directory",
                                                              directory, 
                                                              memory_control)
-  end
-
-  if protocol == "MESI_CMP_directory"
+  elsif protocol == "MESI_CMP_directory"
     net_ports << MESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s,
                                                              "Directory",
                                                              directory,
@@ -124,9 +118,7 @@ num_dma.times { |n|
     net_ports << MOESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
                                                        "DMA",
                                                        dma_sequencer)
-  end
-
-  if protocol == "MESI_CMP_directory"
+  elsif protocol == "MESI_CMP_directory"
     net_ports << MESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
                                                        "DMA",
                                                        dma_sequencer)
diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb
index e6bc1b831..9ec0df252 100644
--- a/src/mem/ruby/config/cfg.rb
+++ b/src/mem/ruby/config/cfg.rb
@@ -296,9 +296,6 @@ private
 
 end
 
-
-
-
 class CacheController < NetPort
   @@total_cache_controllers = Hash.new
 
@@ -438,27 +435,27 @@ class SetAssociativeCache < Cache
       cacti_args << 360 << 0 << 0 << 0 << 0 << 1 << 1 << 1 << 1 << 0 << 0
       cacti_args << 50 << 10 << 10 << 0 << 1 << 1
 
-#      cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join(" ")
-
-#      IO.popen(cacti_cmd) { |pipe|
-#        str1 = pipe.readline
-#        str2 = pipe.readline
-#        results = str2.split(", ")
-#        if results.size != 61
-#          print "CACTI ERROR: CACTI produced unexpected output.\n"
-#          print "Are you using the version shipped with libruby?\n"
-#          raise Exception
-#        end
-#        latency_ns = results[5].to_f
-#        if (latency_ns == "1e+39")
-#          print "CACTI ERROR:  CACTI was unable to realistically model the cache ",@obj_name,"\n"
-#          print "Either change the cache parameters or manually set the latency values\n"
-#          raise Exception
-#        end
-#        clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
-#        latency_cycles = (latency_ns / clk_period_ns).ceil
-#        @latency = latency_cycles
-#      }
+      cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join(" ")
+
+      IO.popen(cacti_cmd) { |pipe|
+        str1 = pipe.readline
+        str2 = pipe.readline
+        results = str2.split(", ")
+        if results.size != 61
+          print "CACTI ERROR: CACTI produced unexpected output.\n"
+          print "Are you using the version shipped with libruby?\n"
+          raise Exception
+        end
+        latency_ns = results[5].to_f
+        if (latency_ns == "1e+39")
+          print "CACTI ERROR:  CACTI was unable to realistically model the cache ",@obj_name,"\n"
+          print "Either change the cache parameters or manually set the latency values\n"
+          raise Exception
+        end
+        clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
+        latency_cycles = (latency_ns / clk_period_ns).ceil
+        @latency = latency_cycles
+      }
     elsif @latency.is_a?(Float)
       clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
       latency_cycles = (@latency / clk_period_ns).ceil
@@ -757,5 +754,4 @@ class GarnetFlexiblePipeline < GarnetNetwork
   end
 end
 
-#added by SS
 require "defaults.rb"
diff --git a/src/mem/ruby/config/defaults.rb b/src/mem/ruby/config/defaults.rb
index 68617d76b..4e3db4495 100644
--- a/src/mem/ruby/config/defaults.rb
+++ b/src/mem/ruby/config/defaults.rb
@@ -9,7 +9,7 @@ class NetPort < LibRubyObject
 
   # buffer_size limits the size of all other buffers connecting to
   # SLICC Controllers.  When 0, infinite buffering is used.
-  default_param :buffer_size, Integer, 0
+  default_param :buffer_size, Integer, 32
 
   # added by SS for TBE
   default_param :number_of_TBEs, Integer, 256
@@ -36,19 +36,19 @@ class Debug < LibRubyObject
   #   1. change protocol_trace = true
   #   2. enable debug in the Ruby Makefile
   #   3. set start_time = 1
-  default_param :protocol_trace, Boolean, true
+  default_param :protocol_trace, Boolean, false
 
   # a string for filtering debugging output (for all g_debug vars see Debug.h)
-  default_param :filter_string, String, "none"
+  default_param :filter_string, String, ""
 
   # filters debugging messages based on priority (low, med, high)
-  default_param :verbosity_string, String, "none"
+  default_param :verbosity_string, String, ""
 
   # filters debugging messages based on a ruby time
   default_param :start_time, Integer, 1
   
   # sends debugging messages to a output filename
-  default_param :output_filename, String, "debug_ss"
+  default_param :output_filename, String, ""
 end
 
 class Topology < LibRubyObject
@@ -167,6 +167,32 @@ class MOESI_CMP_directory_DMAController < DMAController
   default_param :response_latency, Integer, 14
 end
 
+class MESI_CMP_directory_L2CacheController < CacheController
+  default_param :l2_request_latency, Integer, 2
+  default_param :l2_response_latency, Integer, 2
+  default_param :to_L1_latency, Integer, 1
+
+#if 0 then automatically calculated
+  default_param :lowest_bit, Integer, 0
+  default_param :highest_bit, Integer, 0    
+end
+
+class MESI_CMP_directory_L1CacheController < L1CacheController
+  default_param :l1_request_latency, Integer, 2
+  default_param :l1_response_latency, Integer, 2
+  default_param :to_L2_latency, Integer, 1
+end
+
+
+class MESI_CMP_directory_DirectoryController < DirectoryController
+  default_param :to_mem_ctrl_latency, Integer, 1
+  default_param :directory_latency, Integer, 6
+end
+
+class MESI_CMP_directory_DMAController < DMAController
+  default_param :request_latency, Integer, 6
+end
+
 class RubySystem
 
   # Random seed used by the simulation. If set to "rand", the seed
@@ -206,29 +232,5 @@ class RubySystem
 end
 #added by SS
 
-class MESI_CMP_directory_L2CacheController < CacheController
-  default_param :l2_request_latency, Integer, 2
-  default_param :l2_response_latency, Integer, 2
-  default_param :to_L1_latency, Integer, 1
 
-#if 0 then automatically calculated
-  default_param :lowest_bit, Integer, 0
-  default_param :highest_bit, Integer, 0    
-end
-
-class MESI_CMP_directory_L1CacheController < L1CacheController
-  default_param :l1_request_latency, Integer, 2
-  default_param :l1_response_latency, Integer, 2
-  default_param :to_L2_latency, Integer, 1
-end
-
-
-class MESI_CMP_directory_DirectoryController < DirectoryController
-  default_param :to_mem_ctrl_latency, Integer, 1
-  default_param :directory_latency, Integer, 6
-end
-
-class MESI_CMP_directory_DMAController < DMAController
-  default_param :request_latency, Integer, 6
-end