ruby: give access to cache tag/data latencies from SLICC

This patch exposes the tag and data array latencies to the SLICC state machines
so that it can be used to determine the correct enqueue latency for response
messages.

3 files changed, 6 insertions, 0 deletions

diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index fb506781c..88b9839bb 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -149,6 +149,8 @@ structure (CacheMemory, external = "yes") {
   void deallocate(Address);
   AbstractCacheEntry lookup(Address);
   bool isTagPresent(Address);
+  Cycles getTagLatency();
+  Cycles getDataLatency();
   void setMRU(Address);
   void recordRequestType(CacheRequestType);
   bool checkResourceAvailable(CacheResourceType, Address);
diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh
index 5cc3eee32..dbfee9994 100644
--- a/src/mem/ruby/structures/BankedArray.hh
+++ b/src/mem/ruby/structures/BankedArray.hh
@@ -70,6 +70,7 @@ class BankedArray
     // This is so we don't get aliasing on blocks being replaced
     bool tryAccess(int64 idx);
 
+    Cycles getLatency() const { return accessLatency; }
 };
 
 #endif
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 4724da2b8..647520566 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -91,6 +91,9 @@ class CacheMemory : public SimObject
     const AbstractCacheEntry* lookup(const Address& address) const;
 
     Cycles getLatency() const { return m_latency; }
+    Cycles getTagLatency() const { return tagArray.getLatency(); }
+    Cycles getDataLatency() const { return dataArray.getLatency(); }
+
 
     // Hook for checkpointing the contents of the cache
     void recordCacheContents(int cntrl, CacheRecorder* tr) const;