Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts

getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28

1 files changed, 1 insertions, 1 deletions

diff --git a/src/mem/request.hh b/src/mem/request.hh
index b01c02441..de0512e1c 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -234,7 +234,7 @@ class Request
     bool isMmapedIpr() { assert(validPaddr); return mmapedIpr; }
 
     /** Accessor function for asi.*/
-    void setMmapedIpr(bool r) { assert(validPaddr); mmapedIpr = r; }
+    void setMmapedIpr(bool r) { assert(validAsidVaddr); mmapedIpr = r; }
 
     /** Accessor function to check if sc result is valid. */
     bool scResultValid() { return validScResult; }