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authorAndreas Hansson <andreas.hansson@arm.com>2012-08-28 14:30:33 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-08-28 14:30:33 -0400
commit0cacf7e8178defce4063b7cfc8a592c595f56fa2 (patch)
treeac2a57952c3d8b87b1a2d0190d26ab149c12f65e /src/mem
parentd53d04473e0d6ca1765f1117072eec59187a7f7b (diff)
downloadgem5-0cacf7e8178defce4063b7cfc8a592c595f56fa2.tar.xz
Clock: Add a Cycles wrapper class and use where applicable
This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time. Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though. This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles. In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words. An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/bridge.cc17
-rw-r--r--src/mem/bridge.hh12
2 files changed, 15 insertions, 14 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index ca3fde0ed..3a185a8eb 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -56,7 +56,7 @@
Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
Bridge& _bridge,
BridgeMasterPort& _masterPort,
- int _delay, int _resp_limit,
+ Cycles _delay, int _resp_limit,
std::vector<Range<Addr> > _ranges)
: SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
delay(_delay), ranges(_ranges.begin(), _ranges.end()),
@@ -68,7 +68,7 @@ Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
Bridge& _bridge,
BridgeSlavePort& _slavePort,
- int _delay, int _req_limit)
+ Cycles _delay, int _req_limit)
: MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
{
@@ -76,9 +76,10 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
Bridge::Bridge(Params *p)
: MemObject(p),
- slavePort(p->name + ".slave", *this, masterPort, p->delay, p->resp_size,
- p->ranges),
- masterPort(p->name + ".master", *this, slavePort, p->delay, p->req_size)
+ slavePort(p->name + ".slave", *this, masterPort,
+ ticksToCycles(p->delay), p->resp_size, p->ranges),
+ masterPort(p->name + ".master", *this, slavePort,
+ ticksToCycles(p->delay), p->req_size)
{
}
@@ -140,7 +141,7 @@ Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt)
DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size());
- slavePort.schedTimingResp(pkt, curTick() + delay);
+ slavePort.schedTimingResp(pkt, bridge.clockEdge(delay));
return true;
}
@@ -170,7 +171,7 @@ Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt)
assert(outstandingResponses != respQueueLimit);
++outstandingResponses;
retryReq = false;
- masterPort.schedTimingReq(pkt, curTick() + delay);
+ masterPort.schedTimingReq(pkt, bridge.clockEdge(delay));
}
}
@@ -352,7 +353,7 @@ Bridge::BridgeSlavePort::recvRetry()
Tick
Bridge::BridgeSlavePort::recvAtomic(PacketPtr pkt)
{
- return delay + masterPort.sendAtomic(pkt);
+ return delay * bridge.clockPeriod() + masterPort.sendAtomic(pkt);
}
void
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index cf7673c47..c52146463 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -140,7 +140,7 @@ class Bridge : public MemObject
BridgeMasterPort& masterPort;
/** Minimum request delay though this bridge. */
- Tick delay;
+ Cycles delay;
/** Address ranges to pass through the bridge */
AddrRangeList ranges;
@@ -187,12 +187,12 @@ class Bridge : public MemObject
* @param _name the port name including the owner
* @param _bridge the structural owner
* @param _masterPort the master port on the other side of the bridge
- * @param _delay the delay from seeing a response to sending it
+ * @param _delay the delay in cycles from receiving to sending
* @param _resp_limit the size of the response queue
* @param _ranges a number of address ranges to forward
*/
BridgeSlavePort(const std::string& _name, Bridge& _bridge,
- BridgeMasterPort& _masterPort, int _delay,
+ BridgeMasterPort& _masterPort, Cycles _delay,
int _resp_limit, std::vector<Range<Addr> > _ranges);
/**
@@ -255,7 +255,7 @@ class Bridge : public MemObject
BridgeSlavePort& slavePort;
/** Minimum delay though this bridge. */
- Tick delay;
+ Cycles delay;
/**
* Request packet queue. Request packets are held in this
@@ -286,11 +286,11 @@ class Bridge : public MemObject
* @param _name the port name including the owner
* @param _bridge the structural owner
* @param _slavePort the slave port on the other side of the bridge
- * @param _delay the delay from seeing a request to sending it
+ * @param _delay the delay in cycles from receiving to sending
* @param _req_limit the size of the request queue
*/
BridgeMasterPort(const std::string& _name, Bridge& _bridge,
- BridgeSlavePort& _slavePort, int _delay,
+ BridgeSlavePort& _slavePort, Cycles _delay,
int _req_limit);
/**