summaryrefslogtreecommitdiff
path: root/src/mem
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2015-09-25 07:26:58 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-09-25 07:26:58 -0400
commita9a7002a3b3ad1e423d16ace826e80574d4ddc4f (patch)
tree9af35cf62d5cbbabd296c7bd579bf8eb6bf87f7d /src/mem
parent012dd52dc2e7f6d1b3b31dd0ce34361f54615779 (diff)
downloadgem5-a9a7002a3b3ad1e423d16ace826e80574d4ddc4f.tar.xz
mem: Add check for block status on WriteLineReq fill
More checks to help with understanding of functionality.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/cache.cc10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index fe715fa6d..71fbb1884 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1657,6 +1657,16 @@ Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks)
blk->status |= BlkSecure;
blk->status |= BlkValid | BlkReadable;
+ // sanity check for whole-line writes, which should always be
+ // marked as writable as part of the fill, and then later marked
+ // dirty as part of satisfyCpuSideRequest
+ if (pkt->cmd == MemCmd::WriteLineReq) {
+ assert(!pkt->sharedAsserted());
+ // at the moment other caches do not respond to the
+ // invalidation requests corresponding to a whole-line write
+ assert(!pkt->memInhibitAsserted());
+ }
+
if (!pkt->sharedAsserted()) {
// we could get non-shared responses from memory (rather than
// a cache) even in a read-only cache, note that we set this