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authorNathan Binkert <binkertn@umich.edu>2007-06-20 08:14:11 -0700
committerNathan Binkert <binkertn@umich.edu>2007-06-20 08:14:11 -0700
commitb47737dde7e9138a7e7511380d785f11417552d0 (patch)
treef3de77e7b3ead10ccc01c23f4eadb9518ba6c909 /src/mem
parent438ec924d65f0ff36a88965b6db0b3d0c4c115b3 (diff)
downloadgem5-b47737dde7e9138a7e7511380d785f11417552d0.tar.xz
Make sure all parameters have default values if they're
supposed to and make sure parameters have the right type. Also make sure that any object that should be an intermediate type has the right options set. --HG-- extra : convert_revision : d56910628d9a067699827adbc0a26ab629d11e93
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/BaseCache.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 32f3f0174..55b68f81f 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -90,3 +90,4 @@ class BaseCache(MemObject):
"Only prefetch on data not on instruction accesses")
cpu_side = Port("Port on side closer to CPU")
mem_side = Port("Port on side closer to MEM")
+ addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")