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authorNilay Vaish <nilay@cs.wisc.edu>2014-03-17 17:40:14 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-03-17 17:40:14 -0500
commitf7e7fa6d90f86cb42c04b8aca0b0eb173d68185f (patch)
treec973a6753a1c839e7ba139c8fe88c2bcc80cbf3a /src/mem
parent11ffa379ab6c9b8a477e45a3ac390f7d60ef6b19 (diff)
downloadgem5-f7e7fa6d90f86cb42c04b8aca0b0eb173d68185f.tar.xz
ruby: remove some of the unnecessary code
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/ruby/common/Global.hh1
-rw-r--r--src/mem/ruby/system/RubyPort.cc5
-rw-r--r--src/mem/ruby/system/RubyPort.hh3
-rw-r--r--src/mem/ruby/system/Sequencer.hh2
-rw-r--r--src/mem/ruby/system/System.hh8
5 files changed, 2 insertions, 17 deletions
diff --git a/src/mem/ruby/common/Global.hh b/src/mem/ruby/common/Global.hh
index 8282f5b01..d3f802963 100644
--- a/src/mem/ruby/common/Global.hh
+++ b/src/mem/ruby/common/Global.hh
@@ -46,4 +46,3 @@ extern std::vector<std::map<uint32_t, AbstractController *> > g_abs_controls;
extern Cycles g_ruby_start;
#endif // __MEM_RUBY_COMMON_GLOBAL_HH__
-
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index fe6a33196..ec1266a90 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -57,15 +57,14 @@ RubyPort::RubyPort(const Params *p)
memSlavePort(csprintf("%s-mem-slave-port", name()), this,
p->ruby_system, p->access_phys_mem, -1),
gotAddrRanges(p->port_master_connection_count), drainManager(NULL),
- ruby_system(p->ruby_system), system(p->system),
- access_phys_mem(p->access_phys_mem)
+ system(p->system), access_phys_mem(p->access_phys_mem)
{
assert(m_version != -1);
// create the slave ports based on the number of connected ports
for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
- i), this, ruby_system, access_phys_mem, i));
+ i), this, p->ruby_system, access_phys_mem, i));
}
// create the master ports based on the number of connected ports
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 38e181165..fffe6bb97 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -49,7 +49,6 @@
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/system/System.hh"
#include "mem/mem_object.hh"
-#include "mem/physical.hh"
#include "mem/tport.hh"
#include "params/RubyPort.hh"
@@ -206,8 +205,6 @@ class RubyPort : public MemObject
std::vector<PioMasterPort *> master_ports;
DrainManager *drainManager;
-
- RubySystem* ruby_system;
System* system;
//
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index d7dc7d151..49fd8b7bb 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -40,8 +40,6 @@
#include "mem/ruby/system/RubyPort.hh"
#include "params/RubySequencer.hh"
-class DataBlock;
-
struct SequencerRequest
{
PacketPtr pkt;
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index de35116d4..594f7e4f5 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -38,7 +38,6 @@
#include "base/callback.hh"
#include "base/output.hh"
#include "mem/packet.hh"
-#include "mem/ruby/common/Global.hh"
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/recorder/CacheRecorder.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
@@ -81,13 +80,6 @@ class RubySystem : public ClockedObject
static uint32_t getMemorySizeBits() { return m_memory_size_bits; }
// Public Methods
- Network*
- getNetwork()
- {
- assert(m_network != NULL);
- return m_network;
- }
-
Profiler*
getProfiler()
{