diff options
author | Nathan Binkert <nate@binkert.org> | 2011-06-02 17:36:21 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2011-06-02 17:36:21 -0700 |
commit | 2b1aa35e209a76515763e7e7d7a0fe6a8267bebf (patch) | |
tree | fde43c1f169789aa6f10fc58bb70678d1230e756 /src/mem | |
parent | f49f384fe415e68096d16e0ef5396136bc97b292 (diff) | |
download | gem5-2b1aa35e209a76515763e7e7d7a0fe6a8267bebf.tar.xz |
scons: rename TraceFlags to DebugFlags
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/SConscript | 34 | ||||
-rw-r--r-- | src/mem/cache/SConscript | 8 | ||||
-rw-r--r-- | src/mem/cache/tags/SConscript | 4 |
3 files changed, 23 insertions, 23 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index a8c42df5a..298e1e09f 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -53,24 +53,24 @@ elif env['TARGET_ISA'] != 'no': Source('page_table.cc') Source('translating_port.cc') -TraceFlag('Bus') -TraceFlag('BusAddrRanges') -TraceFlag('BusBridge') -TraceFlag('LLSC') -TraceFlag('MMU') -TraceFlag('MemoryAccess') +DebugFlag('Bus') +DebugFlag('BusAddrRanges') +DebugFlag('BusBridge') +DebugFlag('LLSC') +DebugFlag('MMU') +DebugFlag('MemoryAccess') -TraceFlag('ProtocolTrace') -TraceFlag('RubyCache') -TraceFlag('RubyDma') -TraceFlag('RubyGenerated') -TraceFlag('RubyMemory') -TraceFlag('RubyNetwork') -TraceFlag('RubyPort') -TraceFlag('RubyQueue') -TraceFlag('RubySlicc') -TraceFlag('RubyStorebuffer') -TraceFlag('RubyTester') +DebugFlag('ProtocolTrace') +DebugFlag('RubyCache') +DebugFlag('RubyDma') +DebugFlag('RubyGenerated') +DebugFlag('RubyMemory') +DebugFlag('RubyNetwork') +DebugFlag('RubyPort') +DebugFlag('RubyQueue') +DebugFlag('RubySlicc') +DebugFlag('RubyStorebuffer') +DebugFlag('RubyTester') CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester', 'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache', diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index 781521d3f..dc2270b08 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -42,7 +42,7 @@ Source('builder.cc') Source('mshr.cc') Source('mshr_queue.cc') -TraceFlag('Cache') -TraceFlag('CachePort') -TraceFlag('CacheRepl') -TraceFlag('HWPrefetch') +DebugFlag('Cache') +DebugFlag('CachePort') +DebugFlag('CacheRepl') +DebugFlag('HWPrefetch') diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript index d640a9f13..a233e9684 100644 --- a/src/mem/cache/tags/SConscript +++ b/src/mem/cache/tags/SConscript @@ -42,5 +42,5 @@ Source('cacheset.cc') SimObject('iic_repl/Repl.py') Source('iic_repl/gen.cc') -TraceFlag('IIC') -TraceFlag('IICMore') +DebugFlag('IIC') +DebugFlag('IICMore') |