diff options
author | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-01-18 14:30:31 -0800 |
---|---|---|
committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-01-18 14:30:31 -0800 |
commit | 4a40ac71f8679ea7c15efb45afd522bf4d3b3e73 (patch) | |
tree | 7ae31986310c950b4e0565cb7f35bcacf4e3634b /src/mem | |
parent | 8b4e8690b73f61ae0bb2cb052ec56f58d1d531e2 (diff) | |
download | gem5-4a40ac71f8679ea7c15efb45afd522bf4d3b3e73.tar.xz |
util: make a generic checkpoint aggregator that can aggregate different cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator.
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/page_table.cc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index 4bc3a4434..88cfdfeb7 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -222,6 +222,16 @@ PageTable::unserialize(Checkpoint *cp, const std::string §ion) entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i)); pTable[vaddr] = *entry; ++i; - } + } + + process->M5_pid = pTable[vaddr].asn; + +#if THE_ISA == ALPHA_ISA + // The IPR_DTB_ASN misc reg must be set in Alpha for the tlb to work + // correctly + int id = process->contextIds[0]; + ThreadContext *tc = process->system->getThreadContext(id); + tc->setMiscRegNoEffect(IPR_DTB_ASN, process->M5_pid << 57); +#endif } |