Merge zizzer.eecs.umich.edu:/bk/newmem/

into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22

5 files changed, 44 insertions, 16 deletions

diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 71067032d..27624b378 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -146,7 +146,7 @@ class Bus : public MemObject
 
         /** Constructor for the BusPort.*/
         BusPort(const std::string &_name, Bus *_bus, int _id)
-            : Port(_name), _onRetryList(false), bus(_bus), id(_id)
+            : Port(_name, _bus), _onRetryList(false), bus(_bus), id(_id)
         { }
 
         bool onRetryList()
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 599958222..47d40a490 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -42,7 +42,7 @@ using namespace std;
 
 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
                                 bool _isCpuSide)
-    : Port(_name), cache(_cache), isCpuSide(_isCpuSide)
+    : Port(_name, _cache), cache(_cache), isCpuSide(_isCpuSide)
 {
     blocked = false;
     waitingOnRetry = false;
diff --git a/src/mem/port.hh b/src/mem/port.hh
index b6eeb9db3..75afc04e6 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -58,6 +58,8 @@
 typedef std::list<Range<Addr> > AddrRangeList;
 typedef std::list<Range<Addr> >::iterator AddrRangeIter;
 
+class MemObject;
+
 /**
  * Ports are used to interface memory objects to
  * each other.  They will always come in pairs, and we refer to the other
@@ -81,10 +83,13 @@ class Port
         memory objects. */
     Port *peer;
 
+    /** A pointer to the MemObject that owns this port. This may not be set. */
+    MemObject *owner;
+
   public:
 
     Port()
-        : peer(NULL)
+        : peer(NULL), owner(NULL)
     { }
 
     /**
@@ -92,9 +97,11 @@ class Port
      *
      * @param _name Port name for DPRINTF output.  Should include name
      * of memory system object to which the port belongs.
+     * @param _owner Pointer to the MemObject that owns this port.
+     * Will not necessarily be set.
      */
-    Port(const std::string &_name)
-        : portName(_name), peer(NULL)
+    Port(const std::string &_name, MemObject *_owner = NULL)
+        : portName(_name), peer(NULL), owner(_owner)
     { }
 
     /** Return port name (for DPRINTF). */
@@ -112,16 +119,18 @@ class Port
     void setName(const std::string &name)
     { portName = name; }
 
-    /** Function to set the pointer for the peer port.
-        @todo should be called by the configuration stuff (python).
-    */
+    /** Function to set the pointer for the peer port. */
     void setPeer(Port *port);
 
-    /** Function to set the pointer for the peer port.
-        @todo should be called by the configuration stuff (python).
-    */
+    /** Function to get the pointer to the peer port. */
     Port *getPeer() { return peer; }
 
+    /** Function to set the owner of this port. */
+    void setOwner(MemObject *_owner) { owner = _owner; }
+
+    /** Function to return the owner of this port. */
+    MemObject *getOwner() { return owner; }
+
   protected:
 
     /** These functions are protected because they should only be
@@ -247,8 +256,8 @@ class Port
 class FunctionalPort : public Port
 {
   public:
-    FunctionalPort(const std::string &_name)
-        : Port(_name)
+    FunctionalPort(const std::string &_name, MemObject *_owner = NULL)
+        : Port(_name, _owner)
     {}
 
   protected:
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index b9d5cbe4a..086d91279 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -44,6 +44,7 @@ SimpleTimingPort::recvFunctional(PacketPtr pkt)
         if (target->intersect(pkt))
             done = fixPacket(pkt, target);
 
+        i++;
     }
 
     //Then just do an atomic access and throw away the returned latency
@@ -98,11 +99,29 @@ SimpleTimingPort::recvRetry()
 void
 SimpleTimingPort::sendTiming(PacketPtr pkt, Tick time)
 {
+    // Nothing is on the list: add it and schedule an event
     if (transmitList.empty()) {
         assert(!sendEvent.scheduled());
         sendEvent.schedule(curTick+time);
+        transmitList.push_back(std::pair<Tick,PacketPtr>(time+curTick,pkt));
+        return;
+    }
+
+    // something is on the list and this belongs at the end
+    if (time+curTick >= transmitList.back().first) {
+        transmitList.push_back(std::pair<Tick,PacketPtr>(time+curTick,pkt));
+        return;
+    }
+    // Something is on the list and this belongs somewhere else
+    std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin();
+    std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end();
+    bool done = false;
+
+    while (i != end && !done) {
+        if (time+curTick < i->first)
+            transmitList.insert(i,std::pair<Tick,PacketPtr>(time+curTick,pkt));
+        i++;
     }
-    transmitList.push_back(std::pair<Tick,PacketPtr>(time+curTick,pkt));
 }
 
 void
diff --git a/src/mem/tport.hh b/src/mem/tport.hh
index 438ec56dc..3d28ea3e5 100644
--- a/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@ -114,8 +114,8 @@ class SimpleTimingPort : public Port
 
   public:
 
-    SimpleTimingPort(std::string pname)
-        : Port(pname), sendEvent(this), drainEvent(NULL)
+    SimpleTimingPort(std::string pname, MemObject *_owner = NULL)
+        : Port(pname, _owner), sendEvent(this), drainEvent(NULL)
     {}
 
     /** Hook for draining timing accesses from the system.  The