O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs

This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.

This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.

6 files changed, 28 insertions, 2 deletions

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index ab8b76594..583e60a15 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -52,6 +52,7 @@
 #include "base/trace.hh"
 #include "debug/Bus.hh"
 #include "debug/BusAddrRanges.hh"
+#include "debug/Drain.hh"
 #include "mem/bus.hh"
 
 BaseBus::BaseBus(const BaseBusParams *p)
@@ -246,6 +247,7 @@ BaseBus::Layer<PortClass>::releaseLayer()
         // we see a retry from the destination
         retryWaiting();
     } else if (drainEvent) {
+        DPRINTF(Drain, "Bus done draining, processing drain event\n");
         //If we weren't able to drain before, do it now.
         drainEvent->process();
         // Clear the drain event once we're done with it.
@@ -498,6 +500,7 @@ BaseBus::Layer<PortClass>::drain(Event * de)
     //waiting. We might be idle but have someone waiting if the device we
     //contacted for a retry didn't actually retry.
     if (!retryList.empty() || state != IDLE) {
+        DPRINTF(Drain, "Bus not drained\n");
         drainEvent = de;
         return 1;
     }
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 4ae6376db..c175d5958 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -48,6 +48,7 @@
 #include "cpu/base.hh"
 #include "cpu/smt.hh"
 #include "debug/Cache.hh"
+#include "debug/Drain.hh"
 #include "mem/cache/base.hh"
 #include "mem/cache/mshr.hh"
 #include "sim/full_system.hh"
@@ -752,6 +753,7 @@ BaseCache::drain(Event *de)
         drainEvent = de;
 
         changeState(SimObject::Draining);
+        DPRINTF(Drain, "Cache not drained\n");
         return count;
     }
 
diff --git a/src/mem/packet_queue.cc b/src/mem/packet_queue.cc
index ab50fd567..77fba8883 100644
--- a/src/mem/packet_queue.cc
+++ b/src/mem/packet_queue.cc
@@ -41,6 +41,7 @@
  *          Andreas Hansson
  */
 
+#include "debug/Drain.hh"
 #include "debug/PacketQueue.hh"
 #include "mem/packet_queue.hh"
 
@@ -168,7 +169,9 @@ PacketQueue::scheduleSend(Tick time)
             em.schedule(&sendEvent, std::max(nextReady, curTick() + 1));
     } else {
         // no more to send, so if we're draining, we may be done
-        if (drainEvent && !sendEvent.scheduled()) {
+        if (drainEvent && transmitList.empty() && !sendEvent.scheduled()) {
+            DPRINTF(Drain, "PacketQueue done draining,"
+                    "processing drain event\n");
             drainEvent->process();
             drainEvent = NULL;
         }
@@ -201,6 +204,7 @@ PacketQueue::drain(Event *de)
 {
     if (transmitList.empty() && !sendEvent.scheduled())
         return 0;
+    DPRINTF(Drain, "PacketQueue not drained\n");
     drainEvent = de;
     return 1;
 }
diff --git a/src/mem/port.cc b/src/mem/port.cc
index 36ca6304a..3827994fb 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -82,6 +82,12 @@ MasterPort::getSlavePort() const
 }
 
 void
+MasterPort::unBind()
+{
+    _slavePort = NULL;
+}
+
+void
 MasterPort::bind(SlavePort& slave_port)
 {
     // master port keeps track of the slave port
@@ -167,6 +173,12 @@ SlavePort::~SlavePort()
 }
 
 void
+SlavePort::unBind()
+{
+    _masterPort = NULL;
+}
+
+void
 SlavePort::bind(MasterPort& master_port)
 {
     _masterPort = &master_port;
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 35f2993df..eac92791e 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -140,6 +140,7 @@ class MasterPort : public Port
                PortID id = InvalidPortID);
     virtual ~MasterPort();
 
+    void unBind();
     void bind(SlavePort& slave_port);
     SlavePort& getSlavePort() const;
     bool isConnected() const;
@@ -297,6 +298,7 @@ class SlavePort : public Port
               PortID id = InvalidPortID);
     virtual ~SlavePort();
 
+    void unBind();
     void bind(MasterPort& master_port);
     MasterPort& getMasterPort() const;
     bool isConnected() const;
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index a6eb4d22d..c829bf66e 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -41,6 +41,7 @@
 
 #include "cpu/testers/rubytest/RubyTester.hh"
 #include "debug/Config.hh"
+#include "debug/Drain.hh"
 #include "debug/Ruby.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
@@ -524,8 +525,9 @@ RubyPort::testDrainComplete()
     //If we weren't able to drain before, we might be able to now.
     if (drainEvent != NULL) {
         unsigned int drainCount = getDrainCount(drainEvent);
-        DPRINTF(Config, "Drain count: %u\n", drainCount);
+        DPRINTF(Drain, "Drain count: %u\n", drainCount);
         if (drainCount == 0) {
+            DPRINTF(Drain, "RubyPort done draining, processing drain event\n");
             drainEvent->process();
             // Clear the drain event once we're done with it.
             drainEvent = NULL;
@@ -584,6 +586,7 @@ RubyPort::drain(Event *de)
     if (count != 0) {
         drainEvent = de;
 
+        DPRINTF(Drain, "RubyPort not drained\n");
         changeState(SimObject::Draining);
         return count;
     }