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authorRon Dreslinski <rdreslin@umich.edu>2006-10-20 13:01:21 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-20 13:01:21 -0400
commit28e9641c2cf063d8ee1eba9f440dfcda9c82d965 (patch)
tree27d82f9251fe5b6eb5d4daa94c6b2af00f324229 /src/mem
parent780aa0a0ebb765781a31d0fb58257b1efb1f324a (diff)
downloadgem5-28e9641c2cf063d8ee1eba9f440dfcda9c82d965.tar.xz
Use fixPacket function everywhere.
Fix fixPacket assert function. Stop timing port from forwarding the request if a response was found in its queue on a read. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/python/m5/objects/MemTest.py: Add parameter to configure what percentage of mem accesses are functional src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Use fix Packet function src/mem/packet.cc: Fix an assert that was checking the wrong thing src/mem/tport.cc: Properly detect if we need to do the access to the functional device --HG-- extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/base_cache.cc27
-rw-r--r--src/mem/cache/cache_impl.hh63
-rw-r--r--src/mem/packet.cc2
-rw-r--r--src/mem/tport.cc14
4 files changed, 13 insertions, 93 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index e0301a757..c51f1b6ac 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -116,32 +116,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt)
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->intersect(pkt)) {
- uint8_t* pkt_data;
- uint8_t* write_data;
- int data_size;
- if (target->getAddr() < pkt->getAddr()) {
- int offset = pkt->getAddr() - target->getAddr();
- pkt_data = pkt->getPtr<uint8_t>();
- write_data = target->getPtr<uint8_t>() + offset;
- data_size = target->getSize() - offset;
- assert(data_size > 0);
- if (data_size > pkt->getSize())
- data_size = pkt->getSize();
- } else {
- int offset = target->getAddr() - pkt->getAddr();
- pkt_data = pkt->getPtr<uint8_t>() + offset;
- write_data = target->getPtr<uint8_t>();
- data_size = pkt->getSize() - offset;
- assert(data_size >= pkt->getSize());
- if (data_size > target->getSize())
- data_size = target->getSize();
- }
-
- if (pkt->isWrite()) {
- memcpy(pkt_data, write_data, data_size);
- } else {
- memcpy(write_data, pkt_data, data_size);
- }
+ fixPacket(pkt, target);
}
}
cache->doFunctionalAccess(pkt, isCpuSide);
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index ea30dbba6..a88aeb573 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -560,7 +560,6 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
if (!update) {
// Check for data in MSHR and writebuffer.
if (mshr) {
- warn("Found outstanding miss on an non-update probe");
MSHR::TargetList *targets = mshr->getTargetList();
MSHR::TargetList::iterator i = targets->begin();
MSHR::TargetList::iterator end = targets->end();
@@ -568,71 +567,15 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
Packet * target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
- if (target->isWrite() && target->intersect(pkt)) {
- uint8_t* pkt_data;
- uint8_t* write_data;
- int data_size;
- if (target->getAddr() < pkt->getAddr()) {
- int offset = pkt->getAddr() - target->getAddr();
- pkt_data = pkt->getPtr<uint8_t>();
- write_data = target->getPtr<uint8_t>() + offset;
- data_size = target->getSize() - offset;
- assert(data_size > 0);
- if (data_size > pkt->getSize())
- data_size = pkt->getSize();
- } else {
- int offset = target->getAddr() - pkt->getAddr();
- pkt_data = pkt->getPtr<uint8_t>() + offset;
- write_data = target->getPtr<uint8_t>();
- data_size = pkt->getSize() - offset;
- assert(data_size >= pkt->getSize());
- if (data_size > target->getSize())
- data_size = target->getSize();
- }
-
- if (pkt->isWrite()) {
- memcpy(pkt_data, write_data, data_size);
- } else {
- pkt->flags |= SATISFIED;
- pkt->result = Packet::Success;
- memcpy(write_data, pkt_data, data_size);
- }
+ if (target->intersect(pkt)) {
+ fixPacket(pkt, target);
}
}
}
for (int i = 0; i < writes.size(); ++i) {
Packet * write = writes[i]->pkt;
if (write->intersect(pkt)) {
- warn("Found outstanding write on an non-update probe");
- uint8_t* pkt_data;
- uint8_t* write_data;
- int data_size;
- if (write->getAddr() < pkt->getAddr()) {
- int offset = pkt->getAddr() - write->getAddr();
- pkt_data = pkt->getPtr<uint8_t>();
- write_data = write->getPtr<uint8_t>() + offset;
- data_size = write->getSize() - offset;
- assert(data_size > 0);
- if (data_size > pkt->getSize())
- data_size = pkt->getSize();
- } else {
- int offset = write->getAddr() - pkt->getAddr();
- pkt_data = pkt->getPtr<uint8_t>() + offset;
- write_data = write->getPtr<uint8_t>();
- data_size = pkt->getSize() - offset;
- assert(data_size >= pkt->getSize());
- if (data_size > write->getSize())
- data_size = write->getSize();
- }
-
- if (pkt->isWrite()) {
- memcpy(pkt_data, write_data, data_size);
- } else {
- pkt->flags |= SATISFIED;
- pkt->result = Packet::Success;
- memcpy(write_data, pkt_data, data_size);
- }
-
+ fixPacket(pkt, write);
}
}
if (pkt->isRead()
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index a16e590e3..46c771c48 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -150,7 +150,7 @@ fixPacket(Packet *func, Packet *timing)
Addr timingStart = timing->getAddr();
Addr timingEnd = timing->getAddr() + timing->getSize() - 1;
- assert(!(funcStart > timingEnd || timingStart < funcEnd));
+ assert(!(funcStart > timingEnd || timingStart > funcEnd));
if (DTRACE(FunctionalAccess)) {
DebugOut() << func;
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 2d8e7dba4..479dca1ad 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -33,12 +33,13 @@
void
SimpleTimingPort::recvFunctional(Packet *pkt)
{
- //First check queued events
- std::list<Packet *>::iterator i = transmitList.begin();
- std::list<Packet *>::iterator end = transmitList.end();
- bool cont = true;
+ std::list<Packet *>::iterator i;
+ std::list<Packet *>::iterator end;
- while (i != end && cont) {
+ //First check queued events
+ i = transmitList.begin();
+ end = transmitList.end();
+ while (i != end) {
Packet * target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
@@ -46,8 +47,9 @@ SimpleTimingPort::recvFunctional(Packet *pkt)
fixPacket(pkt, target);
}
+
//Then just do an atomic access and throw away the returned latency
- if (cont)
+ if (pkt->result != Packet::Success)
recvAtomic(pkt);
}