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authorMitch Hayenga <mitch.hayenga@arm.com>2016-04-05 12:39:21 -0500
committerMitch Hayenga <mitch.hayenga@arm.com>2016-04-05 12:39:21 -0500
commit8615b27174ae06db4665016c877b1e88031af203 (patch)
tree7b28888f71e7e41e84d4087b6ccb53670e04582b /src/mem
parent76ee011a12ade238d5cbf4b570e1d34d7ba72687 (diff)
downloadgem5-8615b27174ae06db4665016c877b1e88031af203.tar.xz
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/prefetch/queued.cc3
-rw-r--r--src/mem/request.hh44
2 files changed, 17 insertions, 30 deletions
diff --git a/src/mem/cache/prefetch/queued.cc b/src/mem/cache/prefetch/queued.cc
index 03ca3188f..4bc75acd6 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -122,8 +122,7 @@ QueuedPrefetcher::notify(const PacketPtr &pkt)
pf_pkt->allocate();
if (pkt->req->hasContextId()) {
- pf_req->setThreadContext(pkt->req->contextId(),
- pkt->req->threadId());
+ pf_req->setContext(pkt->req->contextId());
}
if (tagPrefetch && pkt->req->hasPC()) {
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 0d2750a16..90363ea66 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -257,14 +257,13 @@ class Request
VALID_PC = 0x00000010,
/** Whether or not the context ID is valid. */
VALID_CONTEXT_ID = 0x00000020,
- VALID_THREAD_ID = 0x00000040,
/** Whether or not the sc result is valid. */
VALID_EXTRA_DATA = 0x00000080,
/**
* These flags are *not* cleared when a Request object is reused
* (assigned a new address).
*/
- STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID | VALID_THREAD_ID
+ STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
};
private:
@@ -339,10 +338,8 @@ class Request
* store conditional or the compare value for a CAS. */
uint64_t _extraData;
- /** The context ID (for statistics, typically). */
+ /** The context ID (for statistics, locks, and wakeups). */
ContextID _contextId;
- /** The thread ID (id within this CPU) */
- ThreadID _threadId;
/** program counter of initiating access; for tracing/debugging */
Addr _pc;
@@ -363,21 +360,21 @@ class Request
Request()
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{}
Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
- InstSeqNum seq_num, ContextID cid, ThreadID tid)
+ InstSeqNum seq_num, ContextID cid)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
setPhys(paddr, size, flags, mid, curTick());
- setThreadContext(cid, tid);
+ setContext(cid);
privateFlags.set(VALID_INST_SEQ_NUM);
}
@@ -389,7 +386,7 @@ class Request
Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
@@ -399,7 +396,7 @@ class Request
Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
@@ -410,7 +407,7 @@ class Request
Addr pc)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(pc),
+ _extraData(0), _contextId(0), _pc(pc),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
@@ -419,15 +416,15 @@ class Request
}
Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
- Addr pc, ContextID cid, ThreadID tid)
+ Addr pc, ContextID cid)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
setVirt(asid, vaddr, size, flags, mid, pc);
- setThreadContext(cid, tid);
+ setContext(cid);
}
Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
@@ -435,7 +432,7 @@ class Request
: atomicOpFunctor(atomic_op)
{
setVirt(asid, vaddr, size, flags, mid, pc);
- setThreadContext(cid, tid);
+ setContext(cid);
}
~Request()
@@ -446,14 +443,13 @@ class Request
}
/**
- * Set up CPU and thread numbers.
+ * Set up Context numbers.
*/
void
- setThreadContext(ContextID context_id, ThreadID tid)
+ setContext(ContextID context_id)
{
_contextId = context_id;
- _threadId = tid;
- privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID);
+ privateFlags.set(VALID_CONTEXT_ID);
}
/**
@@ -701,14 +697,6 @@ class Request
return _contextId;
}
- /** Accessor function for thread ID. */
- ThreadID
- threadId() const
- {
- assert(privateFlags.isSet(VALID_THREAD_ID));
- return _threadId;
- }
-
void
setPC(Addr pc)
{