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authorGabe Black <gblack@eecs.umich.edu>2010-10-13 01:57:31 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-10-13 01:57:31 -0700
commit930c653270b1523cbeb32a4b48d1fd08eaac6eb8 (patch)
tree57a7c91f46975998626424123edada275e8649fb /src/mem
parentb273e0be33049fc36b386b5ba183f69de53268c2 (diff)
downloadgem5-930c653270b1523cbeb32a4b48d1fd08eaac6eb8.tar.xz
Mem: Change the CLREX flag to CLEAR_LL.
CLREX is the name of an ARM instruction, not a name for this generic flag.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/cache_impl.hh4
-rw-r--r--src/mem/request.hh4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 86bf79b7b..7d19ff7a1 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -306,7 +306,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
int &lat, PacketList &writebacks)
{
if (pkt->req->isUncacheable()) {
- if (pkt->req->isClrex()) {
+ if (pkt->req->isClearLL()) {
tags->clearLocks();
} else {
blk = tags->findBlock(pkt->getAddr());
@@ -449,7 +449,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
}
if (pkt->req->isUncacheable()) {
- if (pkt->req->isClrex()) {
+ if (pkt->req->isClearLL()) {
tags->clearLocks();
} else {
BlkType *blk = tags->findBlock(pkt->getAddr());
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 7149f3199..45551dd03 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -72,7 +72,7 @@ class Request : public FastAlloc
/** This request is to a memory mapped register. */
static const FlagsType MMAPED_IPR = 0x00002000;
/** This request is a clear exclusive. */
- static const FlagsType CLREX = 0x00004000;
+ static const FlagsType CLEAR_LL = 0x00004000;
/** The request should ignore unaligned access faults */
static const FlagsType NO_ALIGN_FAULT = 0x00020000;
@@ -458,7 +458,7 @@ class Request : public FastAlloc
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
- bool isClrex() const { return _flags.isSet(CLREX); }
+ bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
bool
isMisaligned() const